MC54HC245AJD

更新时间： 2024-11-14 13:11:15

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		/
页数	文件大小	规格书
8页	99K
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数据手册

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MC54HC245AJD 数据手册

SEMICONDUCTOR TECHNICAL DATA

High–Performance Silicon–Gate CMOS

J SUFFIX

CERAMIC PACKAGE

CASE 732–03

The MC54/74HC245A is identical in pinout to the LS245. The device

inputs are compatible with standard CMOS outputs; with pullup resistors,

they are compatible with LSTTL outputs.

The HC245A is a 3–state noninverting transceiver that is used for 2–way

asynchronous communication between data buses. The device has an

active–low Output Enable pin, which is used to place the I/O ports into

high–impedance states. The Direction control determines whether data

flows from A to B or from B to A.

N SUFFIX

PLASTIC PACKAGE

CASE 738–03

•

Output Drive Capability: 15 LSTTL Loads

Outputs Directly Interface to CMOS, NMOS, and TTL

Operating Voltage Range: 2 to 6 V

DW SUFFIX

SOIC PACKAGE

CASE 751D–04

Low Input Current: 1 µA

ORDERING INFORMATION

High Noise Immunity Characteristic of CMOS Devices

In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

MC54HCXXXAJ

MC74HCXXXAN

MC74HCXXXADW

Ceramic

Plastic

SOIC

•

Chip Complexity: 308 FETs or 77 Equivalent Gates

LOGIC DIAGRAM

PIN ASSIGNMENT

DIRECTION

OUTPUT ENABLE

DATA

PORT

DATA

PORT

DIRECTION

OUTPUT ENABLE

GND

PIN 10 = GND

PIN 20 = V

FUNCTION TABLE

Control Inputs

Output

Enable

Direction

Operation

Data Transmitted from Bus B to Bus A

Data Transmitted from Bus A to Bus B

Buses Isolated (High–Impedance State)

X = don’t care

2/97

Motorola, Inc. 1997

REV 7

12 3 4 5 6 7 8

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