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MC14556BCPG PDF预览

MC14556BCPG

更新时间: 2024-09-20 04:59:27
品牌 Logo 应用领域
安森美 - ONSEMI 解码器驱动器解复用器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 96K
描述
Dual Binary to 1−of−4 Decoder/Demultiplexer

MC14556BCPG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:DIP
包装说明:ROHS COMPLIANT, PLASTIC, DIP-16针数:16
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:5.35Is Samacsys:N
系列:4000/14000/40000输入调节:STANDARD
JESD-30 代码:R-PDIP-T16JESD-609代码:e3
长度:19.175 mm负载电容(CL):50 pF
逻辑集成电路类型:OTHER DECODER/DRIVER功能数量:2
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE包装方法:RAIL
峰值回流温度(摄氏度):NOT SPECIFIED电源:5/15 V
Prop。Delay @ Nom-Sup:440 ns传播延迟(tpd):440 ns
认证状态:Not Qualified座面最大高度:4.44 mm
子类别:Decoder/Drivers最大供电电压 (Vsup):18 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Matte Tin (Sn) - annealed
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

MC14556BCPG 数据手册

 浏览型号MC14556BCPG的Datasheet PDF文件第2页浏览型号MC14556BCPG的Datasheet PDF文件第3页浏览型号MC14556BCPG的Datasheet PDF文件第4页浏览型号MC14556BCPG的Datasheet PDF文件第5页浏览型号MC14556BCPG的Datasheet PDF文件第6页 
MC14555B, MC14556B  
Dual Binary to 1−of−4  
Decoder/Demultiplexer  
The MC14555B and MC14556B are constructed with  
complementary MOS (CMOS) enhancement mode devices. Each  
Decoder/Demultiplexer has two select inputs (A and B), an active low  
Enable input (E), and four mutually exclusive outputs (Q0, Q1, Q2,  
Q3). The MC14555B has the selected output go to the “high” state,  
and the MC14556B has the selected output go to the “low” state.  
Expanded decoding such as binary−to−hexadecimal (1−of−16), etc.,  
can be achieved by using other MC14555B or MC14556B devices.  
Applications include code conversion, address decoding, memory  
selection control, and demultiplexing (using the Enable input as a data  
input) in digital data transmission systems.  
http://onsemi.com  
MARKING  
DIAGRAMS  
16  
PDIP−16  
MC1455xBCP  
AWLYYWWG  
P SUFFIX  
CASE 648  
1
1
Features  
Diode Protection on All Inputs  
Active High or Active Low Outputs  
Expandable  
16  
SOIC−16  
D SUFFIX  
CASE 751B  
1455xBG  
AWLYWW  
1
1
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
All Outputs Buffered  
16  
Capable of Driving Two Low−Power TTL Loads or One Low−Power  
Schottky TTL Load Over the Rated Temperature Range  
Pb−Free Packages are Available*  
SOEIAJ−16  
F SUFFIX  
CASE 966  
MC1455xB  
ALYWG  
1
1
MAXIMUM RATINGS (Voltages Referenced to V  
)
SS  
x
A
= 5 or 6  
= Assembly Location  
Parameter  
Symbol  
Value  
Unit  
V
WL, L = Wafer Lot  
YY, Y = Year  
WW, W = Work Week  
= Pb−Free Package  
DC Supply Voltage Range  
V
DD  
0.5 to +18.0  
Input or Output Voltage Range  
(DC or Transient)  
V , V  
in out  
0.5 to V  
V
DD  
+ 0.5  
G
Input or Output Current (DC or Transient)  
per Pin  
I , I  
10  
mA  
in out  
PIN ASSIGNMENTS  
MC14555B MC14556B  
Power Dissipation, per Package (Note 1)  
Ambient Temperature Range  
P
D
500  
mW  
°C  
T
A
55 to +125  
65 to +150  
260  
E
1
2
3
4
5
6
7
8
16  
15  
14  
13  
V
E
1
2
3
4
5
6
7
8
16  
15  
14  
13  
V
A
A
A
A
A
A
A
DD  
B
A
A
A
A
A
A
A
DD  
Storage Temperature Range  
T
stg  
°C  
A
B
E
A
E
B
Lead Temperature (8−Second Soldering)  
T
L
°C  
A
B
B
A
B
B
B
Stresses exceeding Maximum Ratings may damage the device. Maximum  
Ratings are stress ratings only. Functional operation above the Recommended  
Operating Conditions is not implied. Extended exposure to stresses above the  
Recommended Operating Conditions may affect device reliability.  
1. Temperature Derating: Plastic “P and D/DW”  
Q0  
Q1  
Q2  
Q3  
V
Q0  
Q1  
Q2  
Q3  
V
B
B
12 Q0  
11 Q1  
10 Q2  
12 Q0  
11 Q1  
10 Q2  
B
B
B
B
B
B
B
B
Packages: – 7.0 mW/°C From 65°C To 125°C  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
9
Q3  
9
Q3  
SS  
SS  
high−impedance circuit. For proper operation, V and V should be constrained  
in  
out  
to the range V v (V or V ) v V  
.
SS  
in  
out  
DD  
Unused inputs must always be tied to an appropriate logic voltage level  
(e.g., either V or V ). Unused outputs must be left open.  
SS  
DD  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
June, 2006 − Rev. 8  
MC14555B/D  
 

MC14556BCPG 替代型号

型号 品牌 替代类型 描述 数据表
MC14556BCP ONSEMI

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