MC14532B
8−Bit Priority Encoder
The MC14532B is constructed with complementary MOS (CMOS)
enhancement mode devices. The primary function of a priority
encoder is to provide a binary address for the active input with the
highest priority. Eight data inputs (D0 thru D7) and an enable input
(E are provided. Five outputs are available, three are address outputs
in)
http://onsemi.com
MARKING
(Q0 thru Q2), one group select (GS) and one enable output (E ).
out
Features
• Diode Protection on All Inputs
DIAGRAMS
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load over the Rated Temperature Range
• Pb−Free Packages are Available*
MC14532BCP
AWLYYWWG
1
MAXIMUM RATINGS (Voltages Referenced to V
)
SS
1
PDIP−16
P SUFFIX
CASE 648
Rating
Symbol
Value
−0.5 to +18.0
Unit
V
DC Supply Voltage Range
V
DD
Input or Output Voltage Range
(DC or Transient)
V ,
−0.5 to V + 0.5
V
in
DD
V
out
Input or Output Current
(DC or Transient) per Pin
I , I
in out
10
mA
Power Dissipation, per Package (Note 1)
Ambient Temperature Range
P
T
500
mW
°C
D
14532BG
AWLYWW
−55 to +125
−65 to +150
260
A
SOIC−16
D SUFFIX
CASE 751B
1
Storage Temperature Range
T
stg
°C
1
Lead Temperature (8 Sec Soldering)
T
°C
L
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
A
WL
= Assembly Location
= Wafer Lot
YY, Y = Year
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
WW = Work Week
G
= Pb−Free Package
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V and V should be constrained
in
out
PIN ASSIGNMENT
to the range V v (V or V ) v V
.
SS
in
out
DD
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V or V ). Unused outputs must be left open.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
D4
D5
D6
D7
V
E
SS
DD
DD
TRUTH TABLE
out
Input
Output
GS
E
D7 D6 D5 D4 D3 D2 D1 D0 GS Q2 Q1 Q0
E
D3
D2
D1
D0
Q0
in
out
0
1
0
1
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
0
0
0
0
0
0
0
0
E
in
Q2
Q1
1
1
1
1
1
0
0
0
X
1
0
0
X
X
1
0
X
X
X
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
1
1
0
0
1
0
1
0
0
0
0
0
V
SS
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
X
1
0
0
X
X
1
0
X
X
X
1
1
1
1
1
0
0
0
0
1
1
0
0
1
0
1
0
0
0
0
0
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
X = Don’t Care
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
April, 2006 − Rev. 6
MC14532B/D