MC14049UB
Hex Buffers
The MC14049UB hex inverter/buffer is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. This complementary MOS device finds primary
use where low power dissipation and/or high noise immunity is
desired. This device provides logic−level conversion using only one
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supply voltage, V . The input−signal high level (V ) can exceed the
DD
IH
V
DD
supply voltage for logic−level conversions. Two TTL/DTL
Loads can be driven when the device is used as CMOS−to−TTL/DTL
MARKING
DIAGRAMS
converters (V = 5.0 V, V v 0.4 V, I ≥ 3.2 mA). Note that pins
DD
OL
OL
13 and 16 are not connected internally on this device; consequently
connections to these terminals will not affect circuit operation.
16
PDIP−16
P SUFFIX
CASE 648
MC14049UBCP
AWLYYWW
Features
1
• High Source and Sink Currents
• High−to−Low Level Converter
• Supply Voltage Range = 3.0 V to 18 V
• Meets JEDEC UB Specifications
• V can exceed V
16
SOIC−16
D SUFFIX
CASE 751B
14049U
AWLYWW
1
IN
DD
• Improved ESD Protection on All Inputs
• Pb−Free Packages are Available*
16
TSSOP−16
DT SUFFIX
CASE 948F
14
049U
ALYW
MAXIMUM RATINGS (Voltages Referenced to V
)
SS
Symbol
Parameter
Value
Unit
1
V
DC Supply Voltage Range
−0.5 to +18.0
−0.5 to +18.0
V
V
DD
16
V
Input Voltage Range
(DC or Transient)
in
SOEIAJ−16
F SUFFIX
CASE 966
MC14049UB
ALYW
V
out
Output Voltage Range
(DC or Transient)
−0.5 to V
+0.5
V
DD
1
I
Input Current
(DC or Transient) per Pin
±10
mA
mA
mW
in
A
= Assembly Location
= Wafer Lot
= Year
I
Output Current
(DC or Transient) per Pin
+45
out
WL, L
YY, Y
P
Power Dissipation, per Package (Note 1)
Plastic
SOIC
D
WW, W = Work Week
825
740
T
Ambient Temperature Range
−55 to +125
−65 to +150
260
°C
°C
°C
A
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
T
stg
Storage Temperature Range
T
Lead Temperature (8−Second Soldering)
L
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits
are exceeded, device functional operation is not implied, damage may occur
and reliability may be affected.
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
1. Temperature Derating: All Packages: See Figure 4.
This device contains circuitry to protect the inputs against damage due to high
static voltages or electric fields referenced to the V pin, only. Extra precautions
SS
must be taken to avoid applications of any voltage higher than the maximum rated
voltages to this high−impedance circuit. For proper operation, the ranges V
v
SS
V
in
v 18 V and V v V v V are recommended.
SS
out
DD
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V or V ). Unused outputs must be left open.
SS
DD
Semiconductor Components Industries, LLC, 2004
1
Publication Order Number:
December, 2004 − Rev. 6
MC14049UB/D