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MC14049UBFR1 PDF预览

MC14049UBFR1

更新时间: 2024-11-04 14:53:11
品牌 Logo 应用领域
安森美 - ONSEMI 输入元件光电二极管逻辑集成电路触发器
页数 文件大小 规格书
8页 205K
描述
4000/14000/40000 SERIES, HEX 1-INPUT INVERT GATE, PDSO16, EIAJ, PLASTIC, SOIC-16

MC14049UBFR1 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP16,.3
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.4
系列:4000/14000/40000JESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:10.2 mm
负载电容(CL):50 pF逻辑集成电路类型:INVERTER
最大I(ol):0.0026 A功能数量:6
输入次数:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:5/15 V
Prop。Delay @ Nom-Sup:120 ns传播延迟(tpd):120 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:2.05 mm子类别:Gates
最大供电电压 (Vsup):18 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:5.275 mm
Base Number Matches:1

MC14049UBFR1 数据手册

 浏览型号MC14049UBFR1的Datasheet PDF文件第2页浏览型号MC14049UBFR1的Datasheet PDF文件第3页浏览型号MC14049UBFR1的Datasheet PDF文件第4页浏览型号MC14049UBFR1的Datasheet PDF文件第5页浏览型号MC14049UBFR1的Datasheet PDF文件第6页浏览型号MC14049UBFR1的Datasheet PDF文件第7页 
The MC14049UB hex inverter/buffer is constructed with MOS  
P–channel and N–channel enhancement mode devices in a single  
monolithic structure. This complementary MOS device finds primary  
use where low power dissipation and/or high noise immunity is  
desired. This device provides logic–level conversion using only one  
http://onsemi.com  
supply voltage, V . The input–signal high level (V ) can exceed the  
DD  
IH  
V
supply voltage for logic–level conversions. Two TTL/DTL  
DD  
MARKING  
DIAGRAMS  
16  
Loads can be driven when the device is used as CMOS–to–TTL/DTL  
converters (V = 5.0 V, V 0.4 V, I 3.2 mA). Note that pins  
DD  
OL  
OL  
13 and 16 are not connected internally on this device; consequently  
connections to these terminals will not affect circuit operation.  
PDIP–16  
P SUFFIX  
CASE 648  
MC14049UBCP  
AWLYYWW  
High Source and Sink Currents  
High–to–Low Level Converter  
Supply Voltage Range = 3.0 V to 18 V  
Meets JEDEC UB Specifications  
V can exceed V  
1
16  
SOIC–16  
D SUFFIX  
CASE 751B  
14049U  
AWLYWW  
IN  
DD  
1
Improved ESD Protection on All Inputs  
16  
TSSOP–16  
DT SUFFIX  
CASE 948F  
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 2.)  
14  
049U  
ALYW  
SS  
Symbol  
Parameter  
Value  
Unit  
V
V
DC Supply Voltage Range  
0.5 to +18.0  
0.5 to +18.0  
DD  
1
V
Input Voltage Range  
(DC or Transient)  
V
in  
16  
SOEIAJ–16  
F SUFFIX  
CASE 966  
V
out  
Output Voltage Range  
(DC or Transient)  
0.5 to V +0.5  
V
DD  
MC14049U  
AWLYWW  
I
Input Current  
(DC or Transient) per Pin  
±10  
mA  
mA  
mW  
in  
1
A
= Assembly Location  
I
Output Current  
(DC or Transient) per Pin  
+45  
out  
WL or L = Wafer Lot  
YY or Y = Year  
WW or W = Work Week  
P
Power Dissipation,  
per Package (Note 3.)  
Plastic  
D
825  
740  
SOIC  
ORDERING INFORMATION  
T
Ambient Temperature Range  
Storage Temperature Range  
55 to +125  
65 to +150  
260  
°C  
°C  
°C  
A
Device  
Package  
PDIP–16  
SOIC–16  
Shipping  
T
stg  
MC14049UBCP  
MC14049UBD  
2000/Box  
2400/Box  
T
Lead Temperature  
(8–Second Soldering)  
L
2. Maximum Ratings are those values beyond which damage to the device  
MC14049UBDR2  
SOIC–16 2500/Tape & Reel  
TSSOP–16 96/Rail  
may occur.  
3. Temperature Derating:  
All Packages: See Figure 4.  
MC14049UBDT  
MC14049UBDTR2 TSSOP–16 2500/Tape & Reel  
This device contains circuitry to protect the inputs against damage due to high  
static voltages or electric fields referenced to the V pin, only. Extra precautions  
mustbetakentoavoidapplicationsofanyvoltagehigherthanthemaximumrated  
MC14049UBF  
SOEIAJ–16  
See Note 1.  
See Note 1.  
SS  
MC14049UBFEL SOEIAJ–16  
voltages to this high–impedance circuit. For proper operation, the ranges V  
SS  
V
18 V and V  
V
V
are recommended.  
in  
SS  
out  
DD  
1. For ordering information on the EIAJ version of  
the SOIC packages, please contact your local  
ON Semiconductor representative.  
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,  
either V or V ). Unused outputs must be left open.  
SS  
DD  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
March, 2000 – Rev. 3  
MC14049UB/D  

MC14049UBFR1 替代型号

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