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MC14050BDG PDF预览

MC14050BDG

更新时间: 2024-11-04 12:22:51
品牌 Logo 应用领域
安森美 - ONSEMI 栅极触发器逻辑集成电路光电二极管PC
页数 文件大小 规格书
9页 148K
描述
Hex Buffer

MC14050BDG 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:SOIC
包装说明:LEAD FREE, PLASTIC, SOIC-16针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:0.7Samacsys Confidence:3
Samacsys Status:ReleasedSamacsys PartID:225149
Samacsys Pin Count:16Samacsys Part Category:Integrated Circuit
Samacsys Package Category:Small Outline PackagesSamacsys Footprint Name:SOIC-16 CASE751B-05
Samacsys Released Date:2015-08-07 09:54:21Is Samacsys:N
系列:4000/14000/40000JESD-30 代码:R-PDSO-G16
JESD-609代码:e3长度:9.9 mm
负载电容(CL):50 pF逻辑集成电路类型:BUFFER
湿度敏感等级:1功能数量:6
输入次数:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:RAIL
峰值回流温度(摄氏度):260电源:5/15 V
Prop。Delay @ Nom-Sup:140 ns传播延迟(tpd):140 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:1.75 mm子类别:Gates
最大供电电压 (Vsup):18 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:3.9 mm
Base Number Matches:1

MC14050BDG 数据手册

 浏览型号MC14050BDG的Datasheet PDF文件第2页浏览型号MC14050BDG的Datasheet PDF文件第3页浏览型号MC14050BDG的Datasheet PDF文件第4页浏览型号MC14050BDG的Datasheet PDF文件第5页浏览型号MC14050BDG的Datasheet PDF文件第6页浏览型号MC14050BDG的Datasheet PDF文件第7页 
MC14049B, MC14050B  
Hex Buffer  
The MC14049B Hex Inverter/Buffer and MC14050B Noninverting  
Hex Buffer are constructed with MOS PChannel and NChannel  
enhancement mode devices in a single monolithic structure. These  
complementary MOS devices find primary use where low power  
dissipation and/or high noise immunity is desired. These devices  
http://onsemi.com  
MARKING  
provide logic level conversion using only one supply voltage, V  
.
DD  
The inputsignal high level (V ) can exceed the V  
supply  
IH  
DD  
voltage for logic level conversions. Two TTL/DTL loads can be driven  
when the devices are used as a CMOStoTTL/DTL converter  
(V = 5.0 V, V v 0.4 V, I 3.2 mA).  
DIAGRAMS  
16  
1
DD  
OL  
OL  
PDIP16  
P SUFFIX  
CASE 648  
MC140xxBCP  
AWLYYWWG  
Note that pins 13 and 16 are not connected internally on these  
devices; consequently connections to these terminals will not affect  
circuit operation.  
Features  
16  
SOIC16  
D SUFFIX  
CASE 751B  
High Source and Sink Currents  
HightoLow Level Converter  
Supply Voltage Range = 3.0 V to 18 V  
V can exceed V  
140xxBG  
AWLYWW  
1
IN  
DD  
16  
Meets JEDEC B Specifications  
14  
050B  
ALYWG  
G
Improved ESD Protection On All Inputs  
These Devices are PbFree and are RoHS Compliant  
TSSOP16  
DT SUFFIX  
CASE 948F  
1
MAXIMUM RATINGS (Voltages Referenced to V  
)
SS  
Symbol  
Parameter  
Value  
Unit  
V
16  
V
DD  
DC Supply Voltage Range  
0.5 to +18.0  
0.5 to +18.0  
SOEIAJ16  
F SUFFIX  
CASE 966  
MC140xxB  
ALYWG  
V
in  
Input Voltage Range (DC or Transient)  
V
V
out  
Output Voltage Range (DC or Transient) 0.5 to V  
+
V
DD  
0.5  
1
I
Input Current (DC or Transient) per Pin  
Output Current (DC or Transient) per Pin  
10  
45  
mA  
mA  
mW  
in  
xx  
A
WL, L  
YY, Y  
= Specific Device Code  
= Assembly Location  
= Wafer Lot  
I
out  
P
Power Dissipation, per Package (Note 1)  
D
(Plastic)  
(SOIC)  
825  
740  
= Year  
WW, W = Work Week  
G or G  
= PbFree Indicator  
T
Ambient Temperature Range  
55 to +125  
65 to +150  
260  
°C  
°C  
°C  
A
(Note: Microdot may be in either location)  
T
stg  
Storage Temperature Range  
T
Lead Temperature (8Second Soldering)  
L
1. Temperature Derating: See Figure 3.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
This device contains protection circuitry to protect the inputs against damage  
due to high static voltages or electric fields referenced to the V pin only. Extra  
SS  
precautions must be taken to avoid applications of any voltage higher than the  
maximum rated voltages to this highimpedance circuit. For proper operation, the  
ranges V V 18 V and V V V are recommended.  
SS  
in  
SS  
out  
DD  
Unused inputs must always be tied to an appropriate logic voltage level  
(e.g., either V or V ). Unused outputs must be left open.  
SS  
DD  
© Semiconductor Components Industries, LLC, 2011  
1
Publication Order Number:  
June, 2011 Rev. 7  
MC14049B/D  
 

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