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MC10H181L

更新时间： 2024-09-21 22:58:11
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 运算电路逻辑集成电路
页数 文件大小 规格书
5页 163K
描述
4-Bit Arithmetic Logic Unit/Function Generator

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中文翻译

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MC10H181L 技术参数

生命周期：Transferred零件包装代码：DIP
包装说明：DIP, DIP24,.3针数：24
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.42Is Samacsys：N
其他特性：CAPABLE OF 16 LOGIC & ARITHMETIC OPERATIONS; INTERNAL RIPPLE CARRY; HIGHER ORDER LOOKAHEAD系列：10H
JESD-30 代码：R-CDIP-T24JESD-609代码：e0
长度：32.07 mm逻辑集成电路类型：ARITHMETIC LOGIC UNIT
位数：4功能数量：1
端子数量：24最高工作温度：75 °C
最低工作温度：输出特性：OPEN-EMITTER
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：DIP
封装等效代码：DIP24,.3封装形状：RECTANGULAR
封装形式：IN-LINE最大电源电流（ICC）：159 mA
传播延迟（tpd）：4.3 ns认证状态：Not Qualified
座面最大高度：5.08 mm子类别：Arithmetic Circuits
表面贴装：NO技术：ECL
温度等级：COMMERCIAL EXTENDED端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL宽度：7.62 mm
Base Number Matches：1

MC10H181L 数据手册

 浏览型号MC10H181L的Datasheet PDF文件第2页浏览型号MC10H181L的Datasheet PDF文件第3页浏览型号MC10H181L的Datasheet PDF文件第4页浏览型号MC10H181L的Datasheet PDF文件第5页 
SEMICONDUCTOR TECHNICAL DATA  
The MC10H181 is a high–speed arithmetic logic unit capable of performing  
16 logic operations and 16 arithmetic operations on two four–bit words. Full  
internal carry is incorporated for ripple through operation.  
Arithmetic logic operations are selected by applying the appropriate binary  
word to the select inputs (S0 through S3) as indicated in the tables of  
L SUFFIX  
CERAMIC PACKAGE  
CASE 758–02  
arithmetic/logic functions. Group carry propagate (P ) and carry generate (G )  
G
G
are provided to allow fast operations on very long words using a second order  
look–ahead. The internal carry is enabled by applying a low level voltage to the  
mode control input (M).  
P SUFFIX  
PLASTIC PACKAGE  
CASE 724–03  
When used with the MC10H179, full–carry look–ahead, as a second order  
look–ahead block, the MC10H181 provides high–speed arithmetic operations  
on very long words.  
This 10H part is a functional/pinout duplication of the standard MECL 10K  
family part with 100% improvement in propagation delay and no increase in  
power supply current.  
FN SUFFIX  
PLCC  
CASE 776–02  
•
Improved Noise Margin, 150 mV (Over Operating Voltage and  
Temperature Range)  
DIP  
•
Voltage Compensated  
• MECL 10K – Compatible  
PIN ASSIGNMENT  
MAXIMUM RATINGS  
V
V
CC2  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
CC1  
Characteristic  
Symbol  
Rating  
Unit  
Vdc  
Vdc  
mA  
Power Supply (V  
= 0)  
V
EE  
–8.0 to 0  
M
C
F0  
2
CC  
Input Voltage (V  
= 0)  
V
I
0 to V  
50  
CC  
EE  
F1  
3
N
Output Current— Continuous  
— Surge  
I
out  
A0  
B0  
G
G
4
100  
Operating Temperature Range  
T
A
0 to +75  
°C  
C
5
N + 4  
Storage Temperature Range— Plastic  
— Ceramic  
T
stg  
–55 to +150  
–55 to +165  
°C  
°C  
B1  
A1  
S1  
A2  
S2  
S0  
S3  
F3  
6
F2  
7
NOTE:  
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,  
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed  
circuitboardandtransverseair flowgreaterthan500Ifpmismaintained. Outputsareterminatedthrough  
a 50–ohm resistor to –2.0 volts.  
P
8
G
B3  
A3  
B2  
9
10  
11  
12  
FUNCTION SELECT TABLE  
Logic Functions  
M is High C = D.C.  
F
Arithmetic Operation  
M is Low C is low  
LOGIC DIAGRAM  
Function Select  
S3 S2 S1 S0  
n
V
F
EE  
13  
15  
17  
14  
L
L
L
L
L
L
L
H
L
F = A  
F = A + B  
F = A + B  
F = Logical “1”  
F = A • B  
F = B  
F = A  
F = A plus (A • B)  
F = A plus (A • B)  
F = A times 2  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion  
Tables on page 6–11 of the Motorola MECL Data  
Book (DL122/D).  
L
L
H
H
L
L
L
H
L
L
H
H
H
H
L
F = (A + B) plus 0  
F = (A + B) plus (A • B)  
F = A plus B  
S0 S1 S2 S3  
L
L
H
L
F0  
F1  
F2  
F3  
2
3
21  
20  
18  
19  
16  
11  
10  
9
A0  
B0  
A1  
B1  
A2  
B2  
A3  
B3  
L
H
H
L
F = A  
B
L
H
L
F = A + B  
F = A plus (A + B)  
F = (A + B) plus 0  
F = A minus B minus 1  
F = (A + B) plus (A • B)  
F = A plus (A + B)  
F = minus 1 (two’s complement)  
F = (A • B) minus 1  
F = (A • B) minus 1  
F = A minus 1  
H
H
H
H
H
H
H
H
F = A • B  
7
6
4
8
L
L
H
L
F = A  
F = B  
B
L
H
H
L
L
H
L
F = A + B  
F = Logical “0”  
F = A • B  
G
G
H
H
H
H
P
G
L
H
L
22  
23  
C
n
M
H
H
F = A • B  
C
5
n+4  
H
F = A  
9/96  
REV 6  
Motorola, Inc. 1996  
12345

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