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MC10H186ALDS PDF预览

MC10H186ALDS

更新时间: 2024-11-09 13:11:15
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MC10H186ALDS 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC10H186 is a hex D type flip–flop with common reset and clock lines.  
This MECL 10H part is a functional/pinout duplication of the standard MECL  
10K family part, with 100% improvement in clock toggle frequency and  
propagation delay and no increase in power–supply current.  
Propagation Delay, 1.7 ns Typical  
Power Dissipation, 460 mW Typical  
Improved Noise Margin 150 mV (Over Operating Voltage and  
Temperature Range)  
L SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
Voltage Compensated  
MECL 10K–Compatible  
P SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
FN SUFFIX  
PLCC  
CASE 775–02  
MAXIMUM RATINGS  
Characteristic  
= 0)  
Symbol  
Rating  
Unit  
Vdc  
Vdc  
mA  
Power Supply (V  
Input Voltage (V  
V
–8.0 to 0  
CC  
= 0)  
EE  
V
I
0 to V  
EE  
CC  
Output Current — Continuous  
— Surge  
I
50  
100  
out  
CLOCKED TRUTH TABLE  
Operating Temperature Range  
T
A
0 to +75  
°C  
R
L
C
D
X
L
Qn+1  
Qn  
L
Storage Temperature Range — Plastic  
— Ceramic  
T
–55 to +150  
–55 to +165  
°C  
°C  
stg  
L
ELECTRICAL CHARACTERISTICS (V  
= –5.2 V ±5%) (See Note)  
L
H *  
H *  
L
EE  
L
H
X
H
0°  
25°  
75°  
H
L
Characteristic  
Symbol  
Min  
Max  
Min  
Max  
Min  
Max  
Unit  
Power Supply Current  
I
121  
110  
121  
mA  
E
* A clock H is a clock transition from  
a low to a high state.  
Input Current High  
Pins 5,6,7,10,11,12  
Pin 9  
I
µA  
inH  
430  
670  
1250  
265  
420  
765  
265  
420  
765  
Pin 1  
Input Current Low  
High Output Voltage  
Low Output Voltage  
High Input Voltage  
Low Input Voltage  
I
0.5  
0.5  
0.3  
µA  
inL  
V
–1.02 –0.84 –0.98 –0.81 –0.92  
–1.95 –1.63 –1.95 –1.63 –1.95  
–1.17 –0.84 –1.13 –0.81 –1.07  
–1.95 –1.48 –1.95 –1.48 –1.95  
–0.735  
–1.60  
Vdc  
Vdc  
Vdc  
Vdc  
OH  
DIP  
V
OL  
PIN ASSIGNMENT  
V
–0.735  
–1.45  
IH  
V
IL  
RESET  
Q0  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
AC PARAMETERS  
Propagation Delay  
Set–up Time  
t
0.7  
1.5  
1.0  
0.7  
0.7  
250  
3.0  
3.0  
0.7  
1.5  
1.0  
0.7  
0.7  
250  
3.0  
3.0  
0.7  
1.5  
1.0  
0.7  
0.7  
250  
3.0  
3.0  
ns  
ns  
Q5  
Q4  
Q3  
D5  
pd  
t
set  
Q1  
Hold Time  
t
ns  
hold  
Q2  
Rise Time  
t
2.6  
2.6  
2.6  
2.6  
2.6  
2.6  
ns  
r
Fall Time  
t
f
ns  
D0  
Toggle Frequency  
f
MHz  
ns  
tog  
D4  
D1  
Reset Recovery Time  
t
rr  
(t  
)
1–9+  
D2  
D3  
NOTE:  
CLOCK  
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,  
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed  
circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated  
through a 50–ohm resistor to –2.0 volts.  
V
EE  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion  
Tables on page 6–11 of the Motorola MECL Data  
Book (DL122/D).  
3/93  
Motorola, Inc. 1996  
REV 5  

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