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MC10H186FNR2 PDF预览

MC10H186FNR2

更新时间: 2024-11-04 05:10:19
品牌 Logo 应用领域
安森美 - ONSEMI 触发器
页数 文件大小 规格书
5页 150K
描述
Hex D Master−Slave Flip−Flop with Reset

MC10H186FNR2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QLCC包装说明:PLASTIC, LCC-20
针数:20Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:8.21
其他特性:RESET ACTIVE ONLY WHEN CLOCK IS LOW系列:10H
JESD-30 代码:S-PQCC-J20JESD-609代码:e0
长度:8.965 mm逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:250000000 Hz位数:6
功能数量:1端子数量:20
最高工作温度:75 °C最低工作温度:
输出特性:OPEN-EMITTER输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC20,.4SQ封装形状:SQUARE
封装形式:CHIP CARRIER包装方法:TAPE AND REEL
峰值回流温度(摄氏度):240最大电源电流(ICC):121 mA
传播延迟(tpd):3 ns认证状态:Not Qualified
座面最大高度:4.57 mm子类别:FF/Latches
表面贴装:YES技术:ECL
温度等级:COMMERCIAL EXTENDED端子面层:Tin/Lead (Sn80Pb20)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
触发器类型:POSITIVE EDGE宽度:8.965 mm
最小 fmax:250 MHzBase Number Matches:1

MC10H186FNR2 数据手册

 浏览型号MC10H186FNR2的Datasheet PDF文件第2页浏览型号MC10H186FNR2的Datasheet PDF文件第3页浏览型号MC10H186FNR2的Datasheet PDF文件第4页浏览型号MC10H186FNR2的Datasheet PDF文件第5页 
MC10H186  
Hex D Master−Slave  
Flip−Flop with Reset  
Description  
The MC10H186 is a hex D type flipflop with common reset and  
clock lines. This MECL 10Hpart is a functional/pinout duplication  
of the standard MECL 10Kfamily part, with 100% improvement in  
clock toggle frequency and propagation delay and no increase in  
powersupply current.  
http://onsemi.com  
MARKING DIAGRAMS*  
Features  
16  
Propagation Delay, 1.7 ns Typical  
Power Dissipation, 460 mW Typical  
MC10H186L  
AWLYYWW  
Improved Noise Margin 150 mV (Over Operating Voltage and  
1
Temperature Range)  
CDIP16  
L SUFFIX  
CASE 620A  
Voltage Compensated  
MECL 10K Compatible  
PbFree Packages are Available*  
CLOCKED TRUTH TABLE  
16  
1
R
L
C
D
X
L
Qn+1  
Qn  
L
MC10H186P  
AWLYYWWG  
L
16  
L
H *  
H *  
L
1
L
H
X
H
PDIP16  
P SUFFIX  
CASE 648  
H
L
* A clock H is a clock transition from  
a low to a high state.  
1 20  
DIP  
PIN ASSIGNMENT  
10H186G  
AWLYYWW  
20  
RESET  
Q0  
V
CC  
1
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Q5  
PLLC20  
FN SUFFIX  
CASE 775  
Q4  
Q1  
Q3  
Q2  
D5  
D0  
A
= Assembly Location  
= Year  
WL, L = Wafer Lot  
YY, Y  
WW, W = Work Week  
G
D4  
D1  
D3  
D2  
= PbFree Package  
CLOCK  
V
EE  
*For additional marking information, refer to  
Application Note AND8002/D.  
Pin assignment is for DualinLine Package.  
For PLCC pin assignment, see the Pin Conversion Tables on page 18  
of the ON Semiconductor MECL Data Book (DL122/D).  
*For additional information on our PbFree strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 3 of this data sheet.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
February, 2006 Rev. 7  
MC10H186/D  

MC10H186FNR2 替代型号

型号 品牌 替代类型 描述 数据表
MC10H176FNR2G ONSEMI

完全替代

Hex D Master−Slave Flip−Flop
MC10H176FNG ONSEMI

完全替代

Hex D Master−Slave Flip−Flop
MC10H131FNG ONSEMI

类似代替

Dual D Type Master−Slave Flip−Flop

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MC10H186LS MOTOROLA

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暂无描述
MC10H186P ONSEMI

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Hex D Master−Slave Flip−Flop with Reset
MC10H186P MOTOROLA

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Hex D Master-Slave Flip-Flop with Reset
MC10H186PDS MOTOROLA

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D Flip-Flop, 6-Func, Master-slave Triggered, ECL, PDIP16
MC10H186PG ONSEMI

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MC10H186PS MOTOROLA

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D Flip-Flop, 6-Func, Master-slave Triggered, ECL, PDIP16