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MC10H161_00 PDF预览

MC10H161_00

更新时间: 2024-11-09 05:10:23
品牌 Logo 应用领域
安森美 - ONSEMI 解码器
页数 文件大小 规格书
8页 138K
描述
Binary to 1-8 Decoder

MC10H161_00 数据手册

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The MC10H161 provides parallel decoding of a three bit binary  
word to one of eight lines. The MC10H161 is useful in high–speed  
multiplexer/demultiplexer applications.  
The MC10H161 is designed to decode a three bit input word to one  
of eight output lines. The MC10H161 output will be low when  
selected while all other output are high. The enable inputs, when either  
or both are high, force all outputs high.  
http://onsemi.com  
MARKING  
DIAGRAMS  
The MC10H161 is a true parallel decoder. This eliminates unequal  
parallel path delay times found in other decoder designs. These  
devices are ideally suited for multiplexer/demultiplexer applications.  
Propagation Delay, 1.0 ns Typical  
16  
CDIP–16  
L SUFFIX  
CASE 620  
MC10H161L  
AWLYYWW  
1
Power Dissipation, 315 mW Typical (same as MECL 10K)  
Improved Noise Margin 150 mV (Over Operating Voltage and  
Temperature Range)  
16  
PDIP–16  
P SUFFIX  
CASE 648  
MC10H161P  
AWLYYWW  
Voltage Compensated  
MECL 10K–Compatible  
1
LOGIC DIAGRAM  
1
E0 2  
E1 15  
PLCC–20  
FN SUFFIX  
CASE 775  
6 Q0  
10H161  
V
= Pin 1  
= Pin 16  
= Pin 8  
CC1  
V
CC2  
5 Q1  
4 Q2  
3 Q3  
13 Q4  
12 Q5  
AWLYYWW  
V
EE  
A 7  
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
B 9  
WW = Work Week  
11 Q6  
10 Q7  
C 14  
ORDERING INFORMATION  
TRUTH TABLE  
ENABLE  
INPUTS  
E1 E0  
Device  
Package  
Shipping  
INPUTS  
OUTPUTS  
C
B
A Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7  
MC10H161L  
CDIP–16  
25 Units/Rail  
L
L
L
L
L
L
L
L
H
X
L
L
L
L
L
L
L
L
X
H
L
L
L
L
L
H
H
L
L
H
L
H
L
H
L
H
X
X
L
H
L
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
MC10H161P  
PDIP–16  
PLCC–20  
25 Units/Rail  
46 Units/Rail  
L
H
H
H
H
X
X
L
MC10H161FN  
H
H
X
X
H
H
DIP PIN ASSIGNMENT  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
V
V
CC2  
E1  
CC1  
E0  
Q3  
Q2  
Q1  
Q0  
A
Pin assignment is for Dual–in–Line  
C
Package. For PLCC pin assignment, see  
the Pin Conversion Tables on page 18 of  
the ON Semiconductor MECL Data  
Book (DL122/D).  
Q4  
Q5  
Q6  
Q7  
B
V
EE  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
March, 2000 – Rev. 6  
MC10H161/D  

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