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MC10H161_06

更新时间： 2024-11-09 05:10:23
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
7页 164K
描述
Binary to 1−8 Decoder (Low)

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MC10H161_06 数据手册

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MC10H161  
Binary to 1−8 Decoder  
(Low)  
Description  
The MC10H161 provides parallel decoding of a three bit binary  
word to one of eight lines. The MC10H161 is useful in high−speed  
multiplexer/demultiplexer applications.  
The MC10H161 is designed to decode a three bit input word to one  
of eight output lines. The MC10H161 output will be low when  
selected while all other output are high. The enable inputs, when either  
or both are high, force all outputs high.  
http://onsemi.com  
MARKING DIAGRAMS*  
16  
The MC10H161 is a true parallel decoder. This eliminates unequal  
parallel path delay times found in other decoder designs. These  
devices are ideally suited for multiplexer/demultiplexer applications.  
MC10H161L  
AWLYYWW  
1
CDIP−16  
L SUFFIX  
CASE 620A  
Features  
• Propagation Delay, 1.0 ns Typical  
• Power Dissipation, 315 mW Typical (same as MECL 10K™)  
• Improved Noise Margin 150 mV (Over Operating Voltage and  
16  
1
Temperature Range)  
MC10H161P  
AWLYYWWG  
16  
• Voltage Compensated  
1
• MECL 10K Compatible  
PDIP−16  
P SUFFIX  
CASE 648  
• Pb−Free Packages are Available*  
DIP PIN ASSIGNMENT  
10H161  
ALYWG  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
V
V
CC2  
CC1  
E0  
E1  
C
Pin assignment is for Dual−in−Line  
Package. For PLCC pin assignment, see  
the Pin Conversion Tables on page 18 of  
the ON Semiconductor MECL Data  
Book (DL122/D).  
Q3  
Q2  
Q1  
Q0  
A
Q4  
SOEIAJ−16  
CASE 966  
Q5  
Q6  
1 20  
Q7  
B
V
EE  
10H161G  
AWLYYWW  
20  
1
LOGIC DIAGRAM  
E0ꢀ2  
E1ꢀ15  
TRUTH TABLE  
6ꢀQ0  
PLLC−20  
FN SUFFIX  
CASE 775  
ENABLE  
INPUTS  
E1 E0  
V
V
= Pin 1  
= Pin 16  
= Pin 8  
CC1  
INPUTS  
OUTPUTS  
CC2  
5ꢀQ1  
C
L
L
L
L
H
H
H
H
X
X
B
L
L
A
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7  
V
EE  
L
L
L
L
L
L
L
L
H
X
L
L
L
L
L
L
L
L
X
H
L
H
L
H
L
H
L
H
X
X
L
H
L
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
4ꢀQ2  
A
= Assembly Location  
= Year  
H
H
L
H
H
H
H
H
H
H
H
Aꢀ7  
Bꢀ9  
3ꢀQ3  
WL, L = Wafer Lot  
YY, Y  
WW, W = Work Week  
G
L
13ꢀQ4  
12ꢀQ5  
H
H
X
X
= Pb−Free Package  
H
H
11ꢀQ6  
10ꢀQ7  
Cꢀ14  
*For additional marking information, refer to  
Application Note AND8002/D.  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
February, 2006 − Rev. 7  
MC10H161/D  
1234567

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