SEMICONDUCTOR TECHNICAL DATA
The MC10H161 provides parallel decoding of a three bit binary word to one
of eight lines. The MC10H161 is useful in high–speed multiplexer/demultiplexer
applications.
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
The MC10H161 is designed to decode a three bit input word to one of eight
output lines. The MC10H161 output will be low when selected while all other
output are high. The enable inputs, when either or both are high, force all
outputs high.
The MC10H161 is a true parallel decoder. This eliminates unequal parallel
path delay times found in other decoder designs. These devices are ideally
suited for multiplexer/demultiplexer applications.
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
•
•
•
Propagation Delay, 1.0 ns Typical
Power Dissipation, 315 mW Typical (same as MECL 10K)
Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
LOGIC DIAGRAM
E0
E1 15
2
6
5
Q0
Q1
•
•
Voltage Compensated
MECL 10K–Compatible
V
V
V
= Pin 1
= Pin 16
= Pin 8
CC1
CC2
EE
4
3
Q2
Q3
A
7
9
MAXIMUM RATINGS
13 Q4
12 Q5
Characteristic
Symbol
Rating
Unit
Vdc
Vdc
mA
B
Power Supply (V
= 0)
V
EE
–8.0 to 0
CC
Input Voltage (V
= 0)
V
I
0 to V
EE
11 Q6
10 Q7
CC
Output Current— Continuous
— Surge
I
50
100
out
C
14
TRUTH TABLE
Operating Temperature Range
T
0 to +75
°C
A
ENABLE
INPUTS
E1 E0
INPUTS
OUTPUTS
Storage Temperature Range— Plastic
— Ceramic
T
stg
–55 to +150
–55 to +165
°C
°C
C
B
A Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
L
L
L
L
L
L
L
L
H
X
L
L
L
L
L
L
L
L
X
H
L
L
L
L
L
H
H
L
L
H
L
H
L
H
L
H
X
X
L
H
L
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
ELECTRICAL CHARACTERISTICS (V
0°
= –5.2 V ±5%) (See Note)
H
H
H
H
H
H
H
H
EE
L
25°
75°
H
H
H
H
X
X
L
Characteristic
Power Supply Current
Input Current High
Input Current Low
High Output Voltage
Low Output Voltage
High Input Voltage
Low Input Voltage
Symbol Min
Max
84
Min
—
Max
76
Min
—
Max
84
Unit
H
H
X
X
I
E
—
—
mA
µA
µA
H
H
I
465
—
—
275
—
—
275
—
inH
I
0.5
0.5
0.3
inL
DIP
V
OH
–1.02 –0.84 –0.98 –0.81 –0.92 –0.735 Vdc
–1.95 –1.63 –1.95 –1.63 –1.95 –1.60 Vdc
–1.17 –0.84 –1.13 –0.81 –1.07 –0.735 Vdc
–1.95 –1.48 –1.95 –1.48 –1.95 –1.45 Vdc
PIN ASSIGNMENT
V
OL
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
V
CC2
CC1
E0
V
IH
E1
V
IL
Q3
Q2
Q1
Q0
A
C
AC PARAMETERS
Q4
Propagation Delay
Data
t
pd
ns
Q5
Q6
0.6
0.8
2.0
2.3
0.65
0.8
2.1
2.4
0.7
0.9
2.2
2.5
Enable
Q7
B
Rise Time
Fall Time
t
0.55
0.55
1.7
1.7
0.65
0.65
1.8
1.8
0.7
0.7
1.9
1.9
ns
ns
r
V
EE
t
f
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,
afterthermalequilibriumhasbeenestablished.Thecircuitisinatestsocketormountedonaprintedcircuit
board and transverse air flow greater than 500 Iinear fpm is maintained. Outputs are terminated through
a 50–ohm resistor to –2.0 volts.
3/93
Motorola, Inc. 1996
REV 5
2–249