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MC10H141FN PDF预览

MC10H141FN

更新时间: 2024-11-12 05:10:23
品牌 Logo 应用领域
安森美 - ONSEMI 移位寄存器触发器逻辑集成电路
页数 文件大小 规格书
6页 149K
描述
Four−Bit Universal Shift Register

MC10H141FN 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QLCC包装说明:PLASTIC, LCC-20
针数:20Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:8.62
Is Samacsys:N计数方向:BIDIRECTIONAL
系列:10HJESD-30 代码:S-PQCC-J20
JESD-609代码:e0长度:8.965 mm
逻辑集成电路类型:PARALLEL IN PARALLEL OUT最大频率@ Nom-Sup:250000000 Hz
湿度敏感等级:1位数:4
功能数量:1端子数量:20
最高工作温度:75 °C最低工作温度:
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC20,.4SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):240传播延迟(tpd):2 ns
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:Shift Registers表面贴装:YES
技术:ECL温度等级:COMMERCIAL EXTENDED
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30触发器类型:POSITIVE EDGE
宽度:8.965 mm最小 fmax:250 MHz
Base Number Matches:1

MC10H141FN 数据手册

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MC10H141  
Four−Bit Universal Shift  
Register  
Description  
The MC10H141 is a fourbit universal shift register. This device is a  
functional/pinout duplication of the standard MECL 10Kpart with  
100% improvement in propagation delay and operation frequency and  
no increase in power supply current.  
http://onsemi.com  
MARKING DIAGRAMS*  
Features  
16  
Shift frequency, 250 MHz Min  
Power Dissipation, 425 mW Typical  
Improved Noise Margin 150 mV (Over Operating Voltage and  
Temperature Range)  
MC10H141L  
AWLYYWW  
1
CDIP16  
L SUFFIX  
CASE 620A  
Voltage Compensated  
MECL 10K Compatible  
PbFree Packages are Available*  
Table 1. TRUTH TABLE  
OUTPUTS  
Q2 Q3  
n + 1 n + 1  
SELECT  
OPERATING  
MODE  
16  
1
S1 S2  
Q0  
Q1  
n + 1  
n + 1  
MC10H141P  
AWLYYWWG  
L
L
Parallel Entry  
D0  
Q1  
D1  
D2  
D3  
16  
L
H
L
Shift Right*  
Shift Left*  
Q2  
Q0  
Q3  
Q1  
DR  
Q2  
n
n
n
n
n
1
H
DL  
Q0  
n
PDIP16  
P SUFFIX  
CASE 648  
H
H
Stop Shift  
Q1  
Q2  
32  
n
n
n
n
*
Outputs as exist after pulse appears at “C” input with  
input conditions as shown (Pulse Positive transition of  
clock input).  
1 20  
10H141G  
AWLYYWW  
20  
1
V
V
CC2  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC1  
Q1  
Q0  
DL  
D0  
D1  
S1  
D2  
Q2  
PLLC20  
FN SUFFIX  
CASE 775  
Q3  
C
DR  
D3  
S2  
A
= Assembly Location  
= Wafer Lot  
WL  
YY  
WW  
G
= Year  
= Work Week  
= PbFree Package  
V
EE  
Pin assignment is for DualinLine Package.  
*For additional marking information, refer to  
Application Note AND8002/D.  
Figure 1. Pin Assignment  
*For additional information on our PbFree strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 3 of this data sheet.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
February, 2006 Rev. 8  
MC10H141/D  

MC10H141FN 替代型号

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