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MC10H145 PDF预览

MC10H145

更新时间: 2024-11-03 22:33:03
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
5页 108K
描述
16 x 4 Bit Register File(RAM)

MC10H145 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC10H145 is a 16 x 4 bit register file. The active-low chip select allows  
easy expansion.  
The operating mode of the register file is controlled by the WE input. When  
WE is “low” the device is in the write mode, the outputs are “low” and the data  
present at D input is stored at the selected address, when WE is “high,” the  
n
device is in the read mode — the data state at the selected location is present  
at the Q outputs.  
n
L SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
Address Access Time, 4.5 ns Typical  
Power Dissipation, 700 mW Typical  
Improved Noise Margin 150 mV (Over Operating Voltage and  
Temperature Range)  
P SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
Voltage Compensated  
MECL 10K-Compatible  
FN SUFFIX  
PLCC  
CASE 775–02  
MAXIMUM RATINGS  
Characteristic  
Symbol  
Rating  
Unit  
Vdc  
Vdc  
mA  
Power Supply (V  
= 0)  
V
EE  
–8.0 to 0  
CC  
TRUTH TABLE  
Input Voltage (V  
= 0)  
V
I
0 to V  
CC  
EE  
Output CurrentContinuous  
— Surge  
I
out  
50  
100  
MODE  
INPUT  
WE  
OUTPUT  
CS  
L
D
L
Q
n
L
n
Operating Temperature Range  
T
0 to +75  
°C  
°C  
A
Write “0”  
Write “1”  
Read  
L
L
Storage Temperature RangePlastic  
— Ceramic  
T
stg  
–55 to +150  
–55 to +165  
L
H
X
X
L
L
H
X
Q
L
ELECTRICAL CHARACTERISTICS (V  
0°  
= –5.2 V ±5%) (See Note)  
EE  
Disabled  
H
25°  
75°  
Characteristic  
Symbol  
Unit  
Q-State of Addressed Cell  
Min  
Max  
160  
375  
Min  
Max  
163  
220  
Min  
Max  
165  
220  
Power Supply Current  
Input Current High  
Input Current Low  
High Output Voltage  
Low Output Voltage  
High Input Voltage  
Low Input Voltage  
NOTE:  
I
mA  
µA  
µA  
E
I
inH  
DIP  
I
0.5  
0.5  
0.3  
PIN ASSIGNMENT  
inL  
V
OH  
–1.02 –0.84 –0.98 –0.81 –0.92 –0.735 Vdc  
–1.95 –1.63 –1.95 –1.63 –1.95 –1.60 Vdc  
–1.17 –0.84 –1.13 –0.81 –1.07 –0.735 Vdc  
–1.95 –1.48 –1.95 –1.48 –1.95 –1.45 Vdc  
V
OL  
Q1  
Q0  
CS  
D1  
D0  
A3  
A2  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
V
IH  
Q2  
Q3  
V
IL  
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,  
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed  
circuitboard and transverse air flow greater than 500 Ifpm is maintained. Outputs are terminated through  
a 50-ohm resistor to –2.0 volts.  
WE  
D3  
D2  
A0  
A1  
V
EE  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion  
Tables on page 6–11 of the Motorola MECL Data  
Book (DL122/D).  
3/93  
Motorola, Inc. 1996  
REV 5  

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