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MC10H113ML1 PDF预览

MC10H113ML1

更新时间： 2024-09-15 21:03:35
品牌 Logo 应用领域
安森美 - ONSEMI 栅输入元件逻辑集成电路石英晶振触发器
页数 文件大小 规格书
3页 96K
描述
IC,LOGIC GATE,QUAD 2-INPUT XOR,ECL,PLASTIC

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MC10H113ML1 技术参数

是否Rohs认证： 符合生命周期：Obsolete
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.82JESD-609代码：e4
逻辑集成电路类型：XOR GATE最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
包装方法：TAPE AND REELProp。Delay @ Nom-Sup：1.9 ns
认证状态：Not Qualified施密特触发器：NO
子类别：Gates技术：ECL
温度等级：COMMERCIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
Base Number Matches：1

MC10H113ML1 数据手册

 浏览型号MC10H113ML1的Datasheet PDF文件第2页浏览型号MC10H113ML1的Datasheet PDF文件第3页 
SEMICONDUCTOR TECHNICAL DATA  
The MC10H113 is a Quad Exclusive OR Gate with an enable common to all  
four gates. The outputs may be wire–ORed together to perform a 4–bit  
comparison function (A = B). The enable is active LOW.  
L SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
•
•
•
Propagation Delay, 1.3 ns Typical  
Power Dissipation 175 mW Typ/Pkg (No Load)  
Improved Noise Margin 150 mV (Over Operating Voltage and  
Temperature Range)  
P SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
•
•
Voltage Compensated  
MECL 10K–Compatible  
FN SUFFIX  
PLCC  
CASE 775–02  
MAXIMUM RATINGS  
Characteristic  
Symbol  
Rating  
Unit  
Vdc  
Vdc  
mA  
Power Supply (V  
= 0)  
V
EE  
–8.0 to 0  
CC  
Input Voltage (V  
= 0)  
V
I
0 to V  
CC  
EE  
LOGIC DIAGRAM  
Output Current— Continuous  
— Surge  
I
out  
50  
100  
E
9
Operating Temperature Range  
T
A
0 to +75  
°C  
4
5
Storage Temperature Range— Plastic  
— Ceramic  
T
–55 to +150  
–55 to +165  
°C  
°C  
stg  
TRUTH TABLE  
2
3
IN  
E
L
OUTPUT  
L
L
L
L
ELECTRICAL CHARACTERISTICS (V  
0°  
= –5.2 V ±5%) (See Note)  
EE  
H
L
H
25°  
75°  
H
H
X
L
H
X
L
L
H
L
L
6
7
Characteristic  
Symbol Min  
Max  
Min  
Max  
Min  
Max  
Unit  
H
Power Supply Current  
I
E
—
46  
—
42  
—
46  
mA  
Input Current High  
Pins 5, 7, 11, 13  
Pins 4, 6, 10, 12  
Pin 9  
I
µA  
inH  
—
—
—
430  
510  
1100  
—
—
—
270  
320  
740  
—
—
—
270  
320  
740  
10  
11  
14  
15  
V
V
V
= PIN 1  
= PIN 16  
= PIN 8  
CC1  
CC2  
EE  
Input Current Low  
High Output Voltage  
Low Output Voltage  
High Input Voltage  
Low Input Voltage  
I
0.5  
—
0.5  
—
0.3  
—
µA  
inL  
V
–1.02 –0.84 –0.98 –0.81 –0.92 –0.735 Vdc  
–1.95 –1.63 –1.95 –1.63 –1.95 –1.60 Vdc  
–1.17 –0.84 –1.13 –0.81 –1.07 –0.735 Vdc  
–1.95 –1.48 –1.95 –1.48 –1.95 –1.45 Vdc  
OH  
12  
13  
V
OL  
V
IH  
V
IL  
AC PARAMETERS  
DIP  
Propagation Delay  
Data  
Enable  
t
pd  
ns  
PIN ASSIGNMENT  
0.4  
0.5  
1.7  
2.3  
0.4  
0.5  
1.8  
2.4  
0.5  
0.6  
1.9  
2.5  
V
A
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
V
CC2  
CC1  
Rise Time  
Fall Time  
NOTE:  
t
0.5  
0.5  
1.8  
1.8  
0.6  
0.6  
1.9  
1.9  
0.6  
0.6  
2.0  
2.0  
ns  
ns  
r
D
C
D
D
C
C
t
OUT  
OUT  
IN  
OUT  
OUT  
f
B
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,  
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed  
circuit board and transverse air flow greater than 500 Iinear fpm is maintained. Outputs are terminated  
through a 50–ohm resistor to –2.0 volts.  
A
IN  
A
IN  
IN  
B
IN  
IN  
BIN  
IN  
ENABLE  
V
EE  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion  
Tables on page 6–11 of the Motorola MECL Data  
Book (DL122/D).  
9/96  
Motorola, Inc. 1996  
REV 6  
123

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