Datasheet > MC10EP32_06

MC10EP32_06

更新时间： 2024-09-17 05:10:23

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
11页	165K
描述
3.3V / 5V ECL ±2 Divider

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MC10EP32_06 数据手册

MC10EP32, MC100EP32

3.3V / 5VꢀECL B2 Divider

Description

The MC10/100EP32 is an integrated B2 divider with differential

CLK inputs.

The V pin, an internally generated voltage supply, is available to

this device only. For single−ended input conditions, the unused

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MARKING DIAGRAMS*

differential input is connected to V as a switching reference voltage.

may also rebias AC coupled inputs. When used, decouple V

and V via a 0.01 mF capacitor and limit current sourcing or sinking

to 0.5 mA. When not used, V should be left open.

HEP32

ALYW

KEP32

ALYW

The reset pin is asynchronous and is asserted on the rising edge.

Upon power−up, the internal flip−flops will attain a random state; the

reset allows for the synchronization of multiple EP32’s in a system.

The 100 Series contains temperature compensation.

SOIC−8

D SUFFIX

CASE 751

Features

• 350 ps Typical Propagation Delay

• Maximum Frequency > 4 GHz Typical (Figure 3)

HP32

KP32

• PECL Mode Operating Range:

ALYWG

TSSOP−8

DT SUFFIX

CASE 948R

= 3.0 V to 5.5 V with V = 0 V

• NECL Mode Operating Range:

= 0 V with V = −3.0 V to −5.5 V

• Open Input Default State

• Safety Clamp on Inputs

• Q Output Will Default LOW with Inputs Open or at V

• Pb−Free Packages are Available

DFN8

MN SUFFIX

CASE 506AA

= MC10

= MC100

= Assembly Location

= Wafer Lot

5P = MC10

3K = MC100

= Year

= Work Week

= Pb−Free Package

= Date Code

(Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D.

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 8 of this data sheet.

Publication Order Number:

December, 2006 − Rev. 10

MC10EP32/D

12 3 4 5 6 7...11

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