The MC10EP33 is an integrated 4 divider. The differential clock
inputs and the V allow a differential, single–ended or AC coupled
BB
interface to the device. If used, the V
output should be bypassed to
BB
ground with a 0.01µF capacitor.
The reset pin is asynchronous and is asserted on the rising edge.
Upon power–up, the internal flip–flops will attain a random state; the
reset allows for the synchronization of multiple EP33’s in a system.
http://onsemi.com
8
• 320ps Propagation Delay
• 3 GHz Typical Toggle Frequency
1
• PECL mode: 3.0V to 5.5V V
with V = 0V
CC
EE
SO–8
D SUFFIX
CASE 751
• ECL mode: 0V V
CC
with V = –3.0V to –5.5V
EE
• Internal Input Resistors: Pulldown on D, D
• Q Output will default LOW with inputs open or at V
• ESD Protection: >4KV HBM, >200V MM
MARKING DIAGRAM
EE
8
1
• V Output
A = Assembly Location
L = Wafer Lot
Y = Year
BB
HEP33
ALYW
• New Differential Input Common Mode Range
• Moisture Sensitivity Level 1, Indefinite Time Out of Drypack
• Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
W = Work Week
*For additional information, see Application Note
AND8002/D
• Transistor Count = 91 devices
PIN DESCRIPTION
PIN
FUNCTION
RESET 1
8
7
V
CC
CLK, CLK
Reset
ECL Clock Inputs
ECL Asynchronous Reset
Reference Voltage Output
ECL Data Outputs
R
4
V
BB
Q, Q
CLK
CLK
2
3
Q
Q
V
CC
Positive Supply
V
EE
Negative, 0 Supply
6
5
TRUTH TABLE
V
BB
4
V
EE
CLK
CLK
RESET
Q
Q
X
Z
X
Z
Z
L
L
F
H
F
Figure 1. 8–Lead Pinout (Top View) and Logic Diagram
Z = LOW to HIGH Transition
Z = HIGH to LOW Transition
F = Divide by 4 Function
ORDERING INFORMATION
Device
Package
Shipping
MC10EP33D
SOIC
98 Units/Rail
MC10EP33DR2
SOIC
2500 Tape & Reel
Semiconductor Components Industries, LLC, 1999
1
Publication Order Number:
December, 1999 – Rev. 1
MC10EP33/D