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MC10EP31MNR4G PDF预览

MC10EP31MNR4G

更新时间: 2024-09-17 05:10:23
品牌 Logo 应用领域
安森美 - ONSEMI 触发器锁存器逻辑集成电路
页数 文件大小 规格书
11页 159K
描述
3.3V / 5V ECL D Flip−Flop with Set and Reset

MC10EP31MNR4G 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:DFN
包装说明:LEAD FREE, DFN-8针数:8
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:5.67
Is Samacsys:N其他特性:NECL MODE: VCC = 0V WITH VEE = -3.0V TO -5.5V
系列:10EJESD-30 代码:S-XDSO-N8
JESD-609代码:e4长度:2 mm
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:3000000000 Hz
湿度敏感等级:1位数:1
功能数量:1端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:COMPLEMENTARY封装主体材料:UNSPECIFIED
封装代码:HVSON封装等效代码:SOLCC8,.08,20
封装形状:SQUARE封装形式:SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:-5.2 V最大电源电流(ICC):47 mA
传播延迟(tpd):0.41 ns认证状态:Not Qualified
座面最大高度:1 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:ECL温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:NO LEAD
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40触发器类型:POSITIVE EDGE
宽度:2 mmBase Number Matches:1

MC10EP31MNR4G 数据手册

 浏览型号MC10EP31MNR4G的Datasheet PDF文件第2页浏览型号MC10EP31MNR4G的Datasheet PDF文件第3页浏览型号MC10EP31MNR4G的Datasheet PDF文件第4页浏览型号MC10EP31MNR4G的Datasheet PDF文件第5页浏览型号MC10EP31MNR4G的Datasheet PDF文件第6页浏览型号MC10EP31MNR4G的Datasheet PDF文件第7页 
MC10EP31, MC100EP31  
3.3V / 5VꢀECL D Flip−Flop  
with Set and Reset  
Description  
The MC10/100EP31 is a D flipflop with set and reset. The device  
is pin and functionally equivalent to the EL31 and LVEL31 devices.  
With AC performance much faster than the EL31 and LVEL31  
devices, the EP31 is ideal for applications requiring the fastest AC  
performance available. Both set and reset inputs are asynchronous,  
level triggered signals. Data enters the master portion of the flipflop  
when CLK is low and is transferred to the slave, and thus the outputs,  
upon a positive transition of the CLK.  
http://onsemi.com  
MARKING DIAGRAMS*  
8
8
8
HEP31  
ALYW  
G
KEP31  
ALYW  
G
1
SOIC8  
D SUFFIX  
CASE 751  
Features  
1
1
The 100 Series contains temperature compensation.  
340 ps Typical Propagation Delay  
Maximum Frequency > 3 GHz Typical  
PECL Mode Operating Range:  
8
8
1
8
1
HP31  
KP31  
V
= 3.0 V to 5.5 V with V = 0 V  
CC  
EE  
ALYWG  
ALYWG  
TSSOP8  
DT SUFFIX  
CASE 948R  
G
G
NECL Mode Operating Range:  
= 0 V with V = 3.0 V to 5.5 V  
1
V
CC  
EE  
Open Input Default State  
Q Output Will Default LOW with Inputs Open or at V  
PbFree Packages are Available  
EE  
1
4
1
4
DFN8  
MN SUFFIX  
CASE 506AA  
H
K
= MC10  
= MC100  
A
L
= Assembly Location  
= Wafer Lot  
5O = MC10  
3J = MC100  
Y
W
G
= Year  
= Work Week  
= PbFree Package  
M
= Date Code  
(Note: Microdot may be in either location)  
*For additional marking information, refer to  
Application Note AND8002/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 7 of this data sheet.  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
December, 2006 Rev. 9  
MC10EP31/D  

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