MC10EP195

更新时间： 2024-09-16 22:40:47

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
20页	130K
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3.3V ECL Programmable Delay Chip

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MC10EP195 数据手册

MC10EP195, MC100EP195

3.3V ECL Programmable

Delay Chip

The MC10/100EP195 is a Programmable Delay Chip (PDC)

designed primarily for clock deskewing and timing adjustment. It

provides variable delay of a differential NECL/PECL input transition.

The delay section consists of a programmable matrix of gates and

multiplexers as shown in the logic diagram, Figure 2. The delay

increment of the EP195 has a digitally selectable resolution of about

10 ps and a net range of up to 10.2 ns. The required delay is selected by

the 10 data select inputs D[9:0] values and controlled by the LEN

(pin 10). A LOW level on LEN allows a transparent LOAD mode of

real time delay values by D[9:0]. A LOW to HIGH transition on LEN

will LOCK and HOLD current values present against any subsequent

changes in D[10:0]. The approximate delay values for varying tap

numbers correlating to D0 (LSB) through D9 (MSB) are shown in

Table 6 and Figure 3.

http://onsemi.com

MARKING

DIAGRAM*

MCXXX

EP195

AWLYYWW

LQFP−32

FA SUFFIX

CASE 873A

Because the EP195 is designed using a chain of multiplexers it has a

fixed minimum delay of 2.2 ns. An additional pin D10 is provided for

controlling Pins 14 and 15, CASCADE and CASCADE, also latched

by LEN, in cascading multiple PDCs for increased programmable

range. The cascade logic allows full control of multiple PDCs.

Switching devices from all “1” states on D[0:9] with SETMAX LOW

to all “0” states on D[0:9] with SETMAX HIGH will increase the

delay equivalent to “D0”, the minimum increment.

XXX

= 10 or 100

= Assembly Location

= Wafer Lot

= Year

= Work Week

*For additional marking information, refer to

Application Note AND8002/D.

Select input pins D[10:0] may be threshold controlled by

combinations of interconnects between V (pin 7) and V (pin 8)

for LVCMOS, ECL, or LVTTL level signals. For LVCMOS input

levels, leave V and V open. For ECL operation, short V and

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 17 of this data sheet.

(pins 7 and 8). For LVTTL level operation, connect a 1.5 V

supply reference to V and leave open V pin. The 1.5 V reference

voltage to V pin can be accomplished by placing a 2.2 kW resistor

between V and V for a 3.3 V power supply.

The V pin, an internally generated voltage supply, is available to

this device only. For single-ended input conditions, the unused

differential input is connected to V as a switching reference voltage.

may also rebias AC coupled inputs. When used, decouple V

and V via a 0.01 mF capacitor and limit current sourcing or sinking

to 0.5 mA. When not used, V should be left open.

The 100 Series contains temperature compensation.

• Maximum Input Clock Frequency >1.2 GHz Typical

• Programmable Range: 0 ns to 10 ns

• Delay Range: 2.2 ns to 12.2 ns

• Open Input Default State

• Safety Clamp on Inputs

• A Logic High on the EN Pin Will Force Q to Logic

Low

• 10 ps Increments

• PECL Mode Operating Range:

• D[10:0] Can Accept Either ECL, LVCMOS, or LVTTL

Inputs

= 3.0 V to 3.6 V with V = 0 V

• V Output Reference Voltage

• NECL Mode Operating Range:

= 0 V with V = −3.0 V to −3.6 V

Semiconductor Components Industries, LLC, 2004

Publication Order Number:

October, 2004 − Rev. 13

MC10EP195/D

12 3 4 5 6 7...20

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与MC10EP195相关器件

型号	品牌	获取价格	描述	数据表
MC10EP195_06	ONSEMI	获取价格	3.3V ECL Programmable Delay Chip
MC10EP195FA	ONSEMI	获取价格	3.3V ECL Programmable Delay Chip
MC10EP195FAG	ONSEMI	获取价格	3.3V ECL Programmable Delay Chip
MC10EP195FAG	ROCHESTER	获取价格	ACTIVE DELAY LINE, COMPLEMENTARY OUTPUT, PQFP32, LEAD FREE, LQFP-32
MC10EP195FAR2	ONSEMI	获取价格	3.3V ECL Programmable Delay Chip
MC10EP195FAR2G	ONSEMI	获取价格	3.3V ECL Programmable Delay Chip
MC10EP195MNG	ONSEMI	获取价格	3.3V ECL Programmable Delay Chip
MC10EP195MNR4G	ONSEMI	获取价格	3.3V ECL Programmable Delay Chip
MC10EP196FAR2	ONSEMI	获取价格	ACTIVE DELAY LINE, COMPLEMENTARY OUTPUT, PQFP32, PLASTIC, LQFP-32
MC10EP29	ONSEMI	获取价格	3.3V / 5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset

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