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MC10EP29DT

更新时间： 2024-11-09 04:17:35
品牌 Logo 应用领域
安森美 - ONSEMI 触发器时钟
页数 文件大小 规格书
11页 173K
描述
3.3V / 5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset

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中文翻译

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MC10EP29DT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP-20针数：20
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：7.9其他特性：NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V
系列：10EJESD-30 代码：R-PDSO-G20
JESD-609代码：e4长度：6.5 mm
逻辑集成电路类型：D FLIP-FLOP位数：1
功能数量：2端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
输出极性：COMPLEMENTARY封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP20,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：RAIL峰值回流温度（摄氏度）：260
电源：-5.2 V最大电源电流（ICC）：60 mA
传播延迟（tpd）：0.5 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：FF/Latches
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：ECL温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40触发器类型：POSITIVE EDGE
宽度：4.4 mmBase Number Matches：1

MC10EP29DT 数据手册

 浏览型号MC10EP29DT的Datasheet PDF文件第2页浏览型号MC10EP29DT的Datasheet PDF文件第3页浏览型号MC10EP29DT的Datasheet PDF文件第4页浏览型号MC10EP29DT的Datasheet PDF文件第5页浏览型号MC10EP29DT的Datasheet PDF文件第6页浏览型号MC10EP29DT的Datasheet PDF文件第7页 
MC10EP29, MC100EP29  
3.3V / 5VꢀECL Dual  
Differential Data and Clock  
D Flip−Flop With Set and  
Reset  
http://onsemi.com  
MARKING  
Description  
The MC10/100EP29 is a dual master−slave flip−flop. The device  
features fully differential Data and Clock inputs as well as outputs.  
The MC10/100EP29 is functionally equivalent to the  
MC10/100EL29. Data enters the master latch when the clock is LOW  
and transfers to the slave upon a positive transition on the clock input.  
The differential inputs have special circuitry which ensures device  
stability under open input conditions. When both differential inputs  
DIAGRAM*  
XXXX  
EP29  
ALYWG  
G
are left open the D input will pull down to V and the D input will  
EE  
TSSOP−20  
DT SUFFIX  
CASE 948E  
bias around V /2. The outputs will go to a defined state, however the  
CC  
state will be random based on how the flip flop powers up.  
Both flip flops feature asynchronous, overriding Set and Reset  
inputs. Note that the Set and Reset inputs cannot both be HIGH  
simultaneously.  
20  
1
XXXX  
EP29  
ALYWG  
G
The V pin, an internally generated voltage supply, is available to  
BB  
this device only. For single-ended input conditions, the unused  
QFN−20  
differential input is connected to V as a switching reference voltage.  
MN SUFFIX  
CASE 485E  
BB  
V
BB  
may also rebias AC coupled inputs. When used, decouple V  
BB  
and V via a 0.01 mF capacitor and limit current sourcing or sinking  
CC  
to 0.5 mA. When not used, V should be left open.  
The 100 Series contains temperature compensation.  
xxx  
A
L
= MC10 or 100  
= Assembly Location  
= Wafer Lot  
BB  
Y
= Year  
= Work Week  
= Pb−Free Package  
Features  
W
G
• Maximum Frequency > 3 GHz Typical  
• 500 ps Typical Propagation Delays  
(Note: Microdot may be in either location)  
• PECL Mode Operating Range: V = 3.0 V to 5.5 V  
CC  
*For additional marking information, refer to  
Application Note AND8002/D.  
with V = 0 V  
EE  
• NECL Mode Operating Range: V = 0 V  
CC  
with V = −3.0 V to −5.5 V  
EE  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 8 of this data sheet.  
• Open Input Default State  
• Safety Clamp on Inputs  
• These are Pb−Free Devices  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
December, 2006 − Rev. 4  
MC10EP29/D  
1234567...11

中文翻译

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MC10EP29DT 替代型号

型号 品牌 替代类型 描述 数据表
MC10EP52MNR4G ONSEMI

类似代替

 3.3V / 5V ECL Differential Data and Clock D Flip−Flop
MC10EP29DTG ONSEMI

类似代替

 3.3V / 5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset
MC10E131FNG ONSEMI

功能相似

 5V ECL 4-Bit D Flip-Flop

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