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MC10EP17DW PDF预览

MC10EP17DW

更新时间: 2024-11-06 22:40:47
品牌 Logo 应用领域
安森美 - ONSEMI 线路驱动器或接收器驱动程序和接口接口集成电路光电二极管
页数 文件大小 规格书
8页 87K
描述
3.3V / 5VECL Quad Differential Driver/Receiver

MC10EP17DW 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOIC-20
针数:20Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:7.71其他特性:CAN ALSO OPERATE WITH -3V TO -5.5V SUPPLY IN NECL MODE
差分输出:YES驱动器位数:4
输入特性:DIFFERENTIAL接口集成电路类型:LINE TRANSCEIVER
接口标准:GENERAL PURPOSEJESD-30 代码:R-PDSO-G20
JESD-609代码:e0长度:12.8 mm
功能数量:4端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):240
电源:+-3.3/+-5 V认证状态:Not Qualified
最大接收延迟:0.3 ns接收器位数:4
座面最大高度:2.65 mm子类别:Line Driver or Receivers
最大压摆率:68 mA最大供电电压:5.5 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:ECL
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn80Pb20)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
最大传输延迟:0.3 ns宽度:7.5 mm
Base Number Matches:1

MC10EP17DW 数据手册

 浏览型号MC10EP17DW的Datasheet PDF文件第2页浏览型号MC10EP17DW的Datasheet PDF文件第3页浏览型号MC10EP17DW的Datasheet PDF文件第4页浏览型号MC10EP17DW的Datasheet PDF文件第5页浏览型号MC10EP17DW的Datasheet PDF文件第6页浏览型号MC10EP17DW的Datasheet PDF文件第7页 
MC10EP17, MC100EP17  
3.3V / 5VĄECL Quad  
Differential Driver/Receiver  
The MC10/100EP17 is a 4-bit differential line receiver based on the  
EP16 device. The >3.0 GHz maximum frequency provided by the high  
frequency outputs makes the device ideal for buffering of very high  
speed oscillators.  
http://onsemi.com  
MARKING  
The V pin, an internally generated voltage supply, is available to  
BB  
this device only. For single-ended input conditions, the unused  
DIAGRAMS*  
differential input is connected to V as a switching reference voltage.  
BB  
V
BB  
may also rebias AC coupled inputs. When used, decouple V  
BB  
20  
and V via a 0.01 mF capacitor and limit current sourcing or sinking  
CC  
20  
to 0.5 mA. When not used, V should be left open.  
BB  
XXXX  
EP17  
ALYW  
1
The design incorporates two stages of gain, internal to the device,  
making it an excellent choice for use in high bandwidth amplifier  
applications.  
TSSOP–20  
DT SUFFIX  
CASE 948E  
1
Inputs of unused gates can be left open and will not affect the  
operation of the rest of the device. All V and V pins must be  
externally connected to power supply to guarantee proper operation.  
The 100 Series contains temperature compensation.  
CC  
EE  
20  
20  
MCXXXEP17  
AWLYYWW  
220 ps Typical Propagation Delay  
1
Maximum Frequency >3.0 GHz Typical  
SO–20  
DW SUFFIX  
CASE 751D  
1
PECL Mode Operating Range: V = 3.0 V to 5.5 V  
CC  
with V = 0 V  
EE  
NECL Mode Operating Range: V = 0 V  
XXXX = MC10 or 100  
CC  
XXX  
A
L,  
WL  
Y, YY  
= 10 or 100  
with V = –3.0 V to –5.5 V  
EE  
= Assembly Location  
= Assembly Lot  
= Wafer Lot  
Open Input Default State  
Safety Clamp on Inputs  
Q Output Will Default LOW with Inputs Open or at V  
= Year  
EE  
W, WW = Work Week  
V Output  
BB  
*For additional information, see Application Note  
AND8002/D  
ORDERING INFORMATION  
Device  
Package  
Shipping  
MC10EP17DT  
TSSOP–20  
75 Units/Rail  
MC10EP17DTR2 TSSOP–20 2500 Tape & Reel  
MC100EP17DT TSSOP–20 75 Units/Rail  
MC100EP17DTR2 TSSOP–20 2500 Tape & Reel  
MC10EP17DW  
SO–20  
38 Units/Rail  
MC10EP17DWR2  
MC100EP17DW  
SO–20  
SO–20  
1000 Tape & Reel  
38 Units/Rail  
MC100EP17DWR2  
SO–20  
1000 Tape & Reel  
Semiconductor Components Industries, LLC, 2002  
1
Publication Order Number:  
September, 2002 – Rev. 4  
MC10EP17/D  

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