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MC10EP17DWR2G PDF预览

MC10EP17DWR2G

更新时间: 2024-11-07 05:10:23
品牌 Logo 应用领域
安森美 - ONSEMI 线路驱动器或接收器驱动程序和接口接口集成电路光电二极管
页数 文件大小 规格书
11页 179K
描述
3.3V / 5V ECL Quad Differential Driver/Receiver

MC10EP17DWR2G 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP20,.4针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.64
Is Samacsys:N其他特性:CAN ALSO OPERATE WITH -3V TO -5.5V SUPPLY IN NECL MODE
差分输出:YES驱动器位数:4
输入特性:DIFFERENTIAL接口集成电路类型:LINE TRANSCEIVER
接口标准:GENERAL PURPOSEJESD-30 代码:R-PDSO-G20
JESD-609代码:e3长度:12.8 mm
湿度敏感等级:3功能数量:4
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:+-3.3/+-5 V
认证状态:Not Qualified最大接收延迟:0.3 ns
接收器位数:4座面最大高度:2.65 mm
子类别:Line Driver or Receivers最大压摆率:68 mA
最大供电电压:5.5 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:ECL温度等级:INDUSTRIAL
端子面层:Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40最大传输延迟:0.3 ns
宽度:7.5 mmBase Number Matches:1

MC10EP17DWR2G 数据手册

 浏览型号MC10EP17DWR2G的Datasheet PDF文件第2页浏览型号MC10EP17DWR2G的Datasheet PDF文件第3页浏览型号MC10EP17DWR2G的Datasheet PDF文件第4页浏览型号MC10EP17DWR2G的Datasheet PDF文件第5页浏览型号MC10EP17DWR2G的Datasheet PDF文件第6页浏览型号MC10EP17DWR2G的Datasheet PDF文件第7页 
MC10EP17, MC100EP17  
3.3V / 5VꢀECL Quad  
Differential Driver/Receiver  
Description  
The MC10/100EP17 is a 4-bit differential line receiver based on the  
EP17 device. The >3.0 GHz maximum frequency provided by the high  
frequency outputs makes the device ideal for buffering of very high  
speed oscillators.  
http://onsemi.com  
MARKING  
DIAGRAMS*  
The V pin, an internally generated voltage supply, is available to  
BB  
this device only. For single-ended input conditions, the unused  
20  
differential input is connected to V as a switching reference voltage.  
BB  
MCXXX  
EP17  
ALYWG  
G
V
BB  
may also rebias AC coupled inputs. When used, decouple V  
BB  
and V via a 0.01 mF capacitor and limit current sourcing or sinking  
CC  
to 0.5 mA. When not used, V should be left open.  
BB  
TSSOP20  
DT SUFFIX  
CASE 948E  
The design incorporates two stages of gain, internal to the device,  
making it an excellent choice for use in high bandwidth amplifier  
applications.  
1
Inputs of unused gates can be left open and will not affect the  
20  
operation of the rest of the device. All V and V pins must be  
CC  
EE  
20  
MCXXXEP17  
AWLYYWWG  
externally connected to power supply to guarantee proper operation.  
The 100 Series contains temperature compensation.  
1
SO20  
DW SUFFIX  
CASE 751D  
1
Features  
220 ps Typical Propagation Delay  
Maximum Frequency >3.0 GHz Typical  
PECL Mode Operating Range: V = 3.0 V to 5.5 V  
CC  
20  
with V = 0 V  
1
EE  
XXXX  
EP17  
ALYWG  
G
NECL Mode Operating Range: V = 0 V  
CC  
with V = 3.0 V to 5.5 V  
QFN20  
EE  
MN SUFFIX  
CASE 485E  
Open Input Default State  
Safety Clamp on Inputs  
Q Output Will Default LOW with Inputs Open or at V  
EE  
XXX  
A
L,  
WL  
Y, YY  
= 10 or 100  
= Assembly Location  
= Assembly Lot  
= Wafer Lot  
V Output  
BB  
PbFree Packages are Available*  
= Year  
W, WW = Work Week  
G or G  
= PbFree Package  
(Note: Microdot may be in either location)  
*For additional marking information, refer to  
Application Note AND8002/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 8 of this data sheet.  
*For additional information on our PbFree strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
December, 2006 Rev. 7  
MC10EP17/D  

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