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MC10159L PDF预览

MC10159L

更新时间: 2024-11-04 04:59:43
品牌 Logo 应用领域
安森美 - ONSEMI 复用器
页数 文件大小 规格书
4页 89K
描述
Quad 2-Input Multiplexer (Inverting)

MC10159L 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP-16针数:16
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.42系列:10K
JESD-30 代码:R-GDIP-T16JESD-609代码:e0
长度:19.495 mm逻辑集成电路类型:MULTIPLEXER
功能数量:4输入次数:2
输出次数:1端子数量:16
最高工作温度:85 °C最低工作温度:-30 °C
输出特性:OPEN-EMITTER输出极性:INVERTED
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:-5.2 V最大电源电流(ICC):58 mA
Prop。Delay @ Nom-Sup:5.3 ns传播延迟(tpd):3.3 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Multiplexer/Demultiplexers表面贴装:NO
技术:ECL温度等级:OTHER
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

MC10159L 数据手册

 浏览型号MC10159L的Datasheet PDF文件第2页浏览型号MC10159L的Datasheet PDF文件第3页浏览型号MC10159L的Datasheet PDF文件第4页 
MC10159  
Quad 2-Input Multiplexer  
(Inverting)  
The MC10159 is a quad two channel multiplexer with enable. It  
incorporates common enable and common data select inputs. The  
select input determines which data inputs are enabled. A high (H) level  
enables data inputs D00, D10, D20, and D30. A low (L) level enables  
data inputs D01, D11, D21, and D31. Any change on the data inputs  
will be reflected at the outputs while the enable is low. Input levels are  
inverted at the output.  
http://onsemi.com  
MARKING  
DIAGRAMS  
P =218 mW typ/pkg (No Load)  
16  
D
CDIP–16  
L SUFFIX  
CASE 620  
t =2.5 ns typ (Data to Q)  
pd  
MC10159L  
AWLYYWW  
3.2 ns typ (Select to Q)  
t , t =2.5 ns typ (20%–80%)  
r
f
1
LOGIC DIAGRAM  
16  
V
= PIN 16  
= PIN 8  
SELECT 9  
PDIP–16  
P SUFFIX  
CASE 648  
CC  
MC10159P  
AWLYYWW  
V
EE  
D01  
D00  
5
6
1
1
Q0  
1
PLCC–20  
FN SUFFIX  
CASE 775  
10159  
D11  
D10  
3
4
AWLYYWW  
2
Q1  
ENABLE 7  
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
WW = Work Week  
D21 12  
15 Q2  
D20 13  
TRUTH TABLE  
D31 10  
D30 11  
14 Q3  
Enable  
Select  
D0  
D1  
Q
L
L
L
L
H
L
X
L
H
X
X
X
H
L
H
L
L
H
H
X
X
L
H
X
DIP PIN ASSIGNMENT  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Q0  
Q1  
V
CC  
L
Q2  
Q3  
D11  
ORDERING INFORMATION  
D10  
D20  
D21  
D30  
D31  
D01  
Device  
Package  
Shipping  
D00  
MC10159L  
CDIP–16  
25 Units / Rail  
ENABLE  
MC10159P  
PDIP–16  
PLCC–20  
25 Units / Rail  
46 Units / Rail  
SELECT  
V
EE  
MC10159FN  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion Tables on page 18  
of the ON Semiconductor MECL Data Book (DL122/D).  
Semiconductor Components Industries, LLC, 2002  
1
Publication Order Number:  
January, 2002 – Rev. 7  
MC10159/D  

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