MC100EP33MNR4G

更新时间： 2024-11-25 05:22:27

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
11页	165K
描述
3.3V / 5V ECL ±4 Divider

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数据手册

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MC100EP33MNR4G 数据手册

MC10EP33, MC100EP33

3.3V / 5VꢀECL B4 Divider

Description

The MC10/100EP33 is an integrated B4 divider. The differential

clock inputs.

The V pin, an internally generated voltage supply, is available to

this device only. For single-ended input conditions, the unused

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differential input is connected to V as a switching reference voltage.

may also rebias AC coupled inputs. When used, decouple V

MARKING

and V via a 0.01 mF capacitor and limit current sourcing or sinking

DIAGRAMS*

to 0.5 mA. When not used, V should be left open.

The reset pin is asynchronous and is asserted on the rising edge.

Upon powerup, the internal flip−flops will attain a random state; the

reset allows for the synchronization of multiple EP33’s in a system.

The 100 Series contains temperature compensation.

HEP33

ALYW

KEP33

ALYW

SOIC−8

D SUFFIX

CASE 751

Features

• 320 ps Propagation Delay

• Maximum Frequency > 4 GHz Typical

• PECL Mode Operating Range: V = 3.0 V to 5.5 V

HP33

KP33

with V = 0 V

ALYWG

TSSOP−8

DT SUFFIX

CASE 948R

• NECL Mode Operating Range: V = 0 V

with V = −3.0 V to −5.5 V

• Open Input Default State

• Safety Clamp on Inputs

• Q Output Will Default LOW with Inputs Open or at V

• V Output

• Pb−Free Packages are Available

DFN8

MN SUFFIX

CASE 506AA

= MC10

= MC100

= Assembly Location

= Wafer Lot

5Q = MC10

3L = MC100

= Year

= Work Week

= Date Code

= Pb−Free Package

(Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D.

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 8 of this data sheet.

Publication Order Number:

December, 2006 − Rev. 9

MC10EP33/D

12 3 4 5 6 7...11

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