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MAX9324

更新时间： 2024-11-12 23:52:11
品牌 Logo 应用领域
美信 - MAXIM 驱动器时钟
页数 文件大小 规格书
12页 273K
描述
One-to-Five LVPECL/LVCMOS Output Clock and Data Driver

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MAX9324 数据手册

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19-2576; Rev 0; 10/02  
One-to-Five LVPECL/LVCMOS Output Clock and  
Data Driver  
General Description  
Features  
The MAX9324 low-skew, low-jitter, clock and data driver  
distributes a differential LVPECL input to four differential  
LVPECL outputs and one single-ended LVCMOS output.  
All outputs default to logic low when the differential inputs  
equal GND or are left open. The MAX9324 operates from  
3.0V to 3.6V, making it ideal for 3.3V systems, and con-  
sumes only 25mA (max) of supply current.  
ꢀ 15ps Differential Output-to-Output Skew  
ꢀ 1.7ps Added Random Jitter  
RMS  
ꢀ 150ps (max) Part-to-Part Skew  
ꢀ 450ps Propagation Delay  
ꢀ Synchronous Output Enable/Disable  
ꢀ Single-Ended Monitor Output  
The MAX9324 features low 150ps (max) part-to-part  
skew, low 15ps output-to-output skew, and low 1.7ps  
RMS jitter, making the device ideal for clock and data  
distribution across a backplane or board. CLK_EN and  
SEOUT_Z control the status of the various outputs.  
Asserting CLK_EN low configures the differential (Q_,  
Q_) outputs to a differential low condition and SEOUT to  
a single-ended logic-low state. CLK_EN operation is  
synchronous with the CLK_ inputs. A logic high on  
SEOUT_Z places SEOUT in a high-impedance state.  
SEOUT_Z is asynchronous with the CLK (CLK) inputs.  
ꢀ Outputs Assert Low when CLK, CLK are Open or  
at GND  
ꢀ 3.0V to 3.6V Supply Voltage Range  
ꢀ -40°C to +85°C Operating Temperature Range  
Ordering Information  
The MAX9324 is available in space-saving 20-pin  
TSSOP and ultra-small 20-pin 4mm ✕ 4mm thin QFN  
packages and operates over the extended (-40°C to  
+85°C) temperature range.  
PART  
MAX9324EUP  
MAX9324ETP*  
TEMP RANGE  
-40°C to +85°C  
-40°C to +85°C  
PIN-PACKAGE  
20 TSSOP  
20 Thin QFN-EP**  
Applications  
*Future product—Contact factory for availability.  
**EP = Exposed paddle.  
Precision Clock Distribution  
Low-Jitter Data Repeater  
Data and Clock Driver and Buffer  
Central-Office Backplane Clock Distribution  
DSLAM Backplane  
Functional Diagram and Typical Operating Circuit appear at  
end of data sheet.  
Base Station  
ATE  
Pin Configurations  
TOP VIEW  
20 19 18 17 16  
GND  
CLK_EN  
N.C.  
1
2
20 Q0  
19 Q0  
V
1
2
3
4
5
15  
14  
13  
12  
11  
SEOUT  
GND  
CC  
3
18 V  
CC  
Q1  
Q1  
Q2  
Q2  
SEOUT  
GND  
4
17 Q1  
16 Q1  
15 Q2  
MAX9324  
N.C.  
MAX9324  
5
**EXPOSED PADDLE  
SEOUT_Z  
CLK  
N.C.  
6
SEOUT_Z  
CLK  
7
14  
13  
Q2  
8
V
CC  
6
7
8
9
10  
CLK  
9
12 Q3  
11 Q3  
V
10  
CC  
THIN QFN-EP** (4mm x 4mm)  
**CONNECT EXPOSED PADDLE TO GND.  
TSSOP  
________________________________________________________________ Maxim Integrated Products  
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at  
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.  
1234567...12

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与MAX9324相关器件

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MAX9324ETP MAXIM

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 		One-to-Five LVPECL/LVCMOS Output Clock and Data Driver
MAX9324EUP MAXIM

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 		One-to-Five LVPECL/LVCMOS Output Clock and Data Driver
MAX9324EUP+ MAXIM

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 		暂无描述
MAX9324EUP+T MAXIM

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 		Low Skew Clock Driver, 4 True Output(s), 0 Inverted Output(s), BICMOS, PDSO20, 4.40 MM, TS
MAX9324EUP-T MAXIM

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 		Low Skew Clock Driver, 4 True Output(s), 0 Inverted Output(s), BICMOS, PDSO20, 4.40 MM, TS
MAX9325 MAXIM

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 		2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver
MAX9325EGI ROCHESTER

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 		9325 SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC28, 5 X 5 M
MAX9325EQI ROCHESTER

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 		9325 SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28, PLASTI
MAX9325EQI+ ROCHESTER

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 		9325 SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28, PLASTI
MAX9325EQI+T MAXIM

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 		Low Skew Clock Driver, 9325 Series, 8 True Output(s), 0 Inverted Output(s), Bipolar, PQCC2

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