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MAX9325EQI+T

更新时间： 2024-09-25 21:20:39
品牌 Logo 应用领域
美信 - MAXIM 驱动逻辑集成电路
页数 文件大小 规格书
12页 730K
描述
Low Skew Clock Driver, 9325 Series, 8 True Output(s), 0 Inverted Output(s), Bipolar, PQCC28, PLASTIC, MO-047AB, LCC-28

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MAX9325EQI+T 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：LCC
包装说明：QCCJ,针数：28
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：20 weeks
风险等级：5.38其他特性：LVECL MODE OPERATING RANGE IS -2.375V TO -3.8V
系列：9325输入调节：DIFFERENTIAL MUX
JESD-30 代码：S-PQCC-J28长度：11.505 mm
逻辑集成电路类型：LOW SKEW CLOCK DRIVER湿度敏感等级：1
功能数量：1反相输出次数：
端子数量：28实输出次数：8
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：NOT SPECIFIED传播延迟（tpd）：0.8 ns
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.05 ns
座面最大高度：4.57 mm最大供电电压 (Vsup)：3.8 V
最小供电电压 (Vsup)：2.375 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：BIPOLAR
温度等级：INDUSTRIAL端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：11.505 mm
Base Number Matches：1

MAX9325EQI+T 数据手册

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19-2511; Rev 3; 11/04  
2:8 Differential LVPECL/LVECL/HSTL Clock and  
Data Driver  
General Description  
Features  
The MAX9325 low-skew, 2:8 differential driver features  
extremely low output-to-output skew (50ps max) and  
part-to-part skew (225ps max). These features make  
the device ideal for clock and data distribution across a  
backplane or board. The device selects one of the two  
differential HSTL or LVECL/LVPECL inputs and repeats  
them at eight differential outputs. Outputs are compati-  
ble with LVECL and LVPECL, and can directly drive  
50Ω terminated transmission lines.  
♦ 50ps (max) Output-to-Output Skew  
♦ 1.5ps (max) Random Jitter  
♦ Guaranteed 300mV Differential Output at 700MHz  
RMS  
♦ +2.375V to +3.8V Supplies for Differential  
HSTL/LVPECL  
♦ -2.375V to -3.8V Supplies for Differential LVECL  
♦ Two Selectable Differential Inputs  
♦ On-Chip Reference for Single-Ended Inputs  
♦ Outputs Low for Inputs Open or at V  
♦ Pin Compatible with MC100LVE310  
The differential inputs can be configured to accept a  
single-ended signal when the unused complementary  
input is connected to the on-chip reference output volt-  
EE  
age V  
EE.  
All inputs have internal pulldown resistors to  
BB.  
V
The internal pulldowns and a fail-safe circuit  
ensure differential low default outputs when the inputs  
are left open or at V  
.
EE  
The MAX9325 operates over a 2.375V to 3.8V supply  
range for interfacing to differential HSTL and LVPECL  
signals. This allows high-performance clock or data dis-  
tribution in systems with a nominal +2.5V or +3.3V sup-  
ply. For LVECL operation, the device operates with a  
-2.375V to -3.8V supply.  
Ordering Information  
PART  
TEMP RANGE  
-40°C to +85°C  
-40°C to +85°C  
PIN-PACKAGE  
28 PLCC  
MAX9325EQI  
MAX9325EGI  
The MAX9325 is offered in 28-lead PLCC and space-  
saving 28-lead QFN packages. The MAX9325 is speci-  
fied for operation from -40°C to +85°C.  
28 QFN 5mm x 5mm  
Applications  
Precision Clock Distribution  
Functional Diagram appears at end of data sheet.  
Low-Jitter Data Repeaters  
Pin Configurations  
TOP VIEW  
INPUT SELECT TRUTH TABLE  
25 24 23 22 21 20 19  
CLK_SEL  
INPUT CLOCK  
*
*
L
CLK0, CLK0 SELECTED  
CLK1, CLK1 SELECTED  
V
EE  
Q3  
Q3  
Q4  
V
26  
27  
28  
1
18  
17  
16  
15  
14  
13  
12  
H
V
1
2
3
4
5
6
7
21 Q3  
20 Q3  
19 Q4  
EE  
CLK_SEL  
CLKO  
CLK_SEL  
CLKO  
V
CC  
CC  
MAX9325  
V
CC  
18  
V
CC  
CLKO  
2
Q4  
Q5  
Q5  
MAX9325  
V
3
CLKO  
17 Q4  
16 Q5  
15 Q5  
BB  
4
CLK1  
V
BB  
CLK1  
5
6
7
8
9
10 11  
*
*
PLCC  
QFN  
*CORNER PINS AND EXPOSED PAD ARE CONNECTED TO V  
.
EE  
________________________________________________________________ Maxim Integrated Products  
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at  
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.  
1234567...12

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