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MAX32520

更新时间: 2023-12-20 18:46:17
品牌 Logo 应用领域
亚德诺 - ADI 微控制器
页数 文件大小 规格书
29页 267K
描述
ChipDNA Secure Arm Cortex M4 Microcontroller

MAX32520 数据手册

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Click here for production status of specific part numbers.  
MAX32520  
ChipDNA Secure Arm Cortex  
M4 Microcontroller  
General Description  
Benefits and Features  
DeepCover® embedded security solutions cloak sensitive  
data under multiple layers of advanced physical security  
to provide the most secure key storage possible.  
● High-Efficiency Microcontroller for Secure Element IoT  
• Arm Cortex-M4F with FPU Up to 120MHz  
• 16KB Unified Code Cache  
• 2MB PUF Encrypted Flash Memory with Cache  
Provides Ultimate Firmware IP Protection  
• Low Latency On-the-Fly Decryption of Flash  
Execution  
• 136KB SRAM + 34KB ECC  
• 8KB User-Programmable OTP  
The DeepCover secure microcontroller MAX32520 pro-  
vides an interoperable, secure, and cost-effective solution  
to build new generations of trusted embedded systems  
and communication devices such as IoT, IoT gateways,  
and wireless access points.  
The MAX32520 incorporates Maxim's patented  
ChipDNA™ PUF technology. ChipDNA technology in-  
volves a physically unclonable function (PUF) that enables  
cost-effective protection against invasive physical attacks.  
Using the random variation of semiconductor device char-  
acteristics that naturally occur during wafer fabrication, the  
ChipDNA circuit generates a unique output value that is  
repeatable over time, temperature, and operating voltage.  
Attempts to probe or observe ChipDNA operation modifies  
the underlying circuit characteristics, preventing discovery  
of the unique value used by the chip cryptographic func-  
tions. The MAX32520 utilizes the ChipDNA output as key  
content to cryptographically secure all device stored da-  
ta including user firmware. User firmware encryption pro-  
vides ultimate software IP protection. The ChipDNA can  
also generate a private key for the ECDSA signing opera-  
tion.  
● Secure Element  
• PUF-Based Keys  
• For Internal Flash Encryption  
• For Strong Device Authentication  
• Secure Boot Loader with Public Key Authentication  
and Serial Flash Emulation  
• AES, SHA, and ECDSA Accelerators  
• Hardware True Random Number Generator  
• SP800-90B Compliant Entropy Source  
• SP800-90A Compliant DRBG  
• Die Shield  
• Temperature and Voltage Tamper Monitor  
• External Tamper Sensor with Random Dynamic  
Pattern  
● Power Management Maximizes Operating Time for  
Battery Applications  
• Single 3.3V/2.5V/1.8V Supply  
• Down to 3.2µA Backup Mode  
• 15µs Wake-Up Time from Standby Mode  
• Clock Gating, Power Gating, Registers, and  
Memory Retention Modes  
The MAX32520 integrates an Arm® Cortex® -M4 proces-  
sor, 2MB of Flash, 136KB of system RAM + 34KB ECC,  
8KB of one-time-programmable (OTP) memory and  
128KB of boot ROM.  
The MAX32520 provides a FIPS/NIST compliant TRNG,  
environmental and tamper detection circuitry to facilitate  
system-level security.  
● Multiple Peripherals for System Control  
• One UART  
2
• One I C Interface  
Multiple high-speed interfaces are supported including  
• QSPI  
2
SPI, UART, and an I C. The four on-chip timers also sup-  
• Four Timers with PWM Capability  
• Up to 27 General-Purpose I/O Pins with Selectable  
Output Driver Strength  
• 4-Channel DMA Controller  
• 4-Pin JTAG  
port PWM output generation for direct control of external  
devices. One of the SPI ports has a serial flash emulation  
mode allowing direct code fetching enabling secure boot  
for a host microcontroller.  
Applications  
Ordering Information appears at end of data sheet.  
● Embedded Connected Systems  
● Secure Industrial Appliances, Sensors, and  
Controllers  
Arm and Cortex are registered trademarks of Arm Limited  
(or its subsidiaries) in the US and/or elsewhere.  
● IoT Nodes and Gateways  
● Embedded Communication Equipment (Routers,  
Gateways, etc.)  
DeepCover is a registered trademark and ChipDNA is a  
trademark of Maxim Integrated Products, Inc.  
● Set-Top Boxes  
19-100583; Rev 0; 6/19  
 
 

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