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MAX32561-LNJ+ PDF预览

MAX32561-LNJ+

更新时间: 2024-11-28 02:52:39
品牌 Logo 应用领域
美信 - MAXIM 微控制器
页数 文件大小 规格书
2页 320K
描述
DeepCover Secure Arm Cortex-M3 Flash Microcontroller

MAX32561-LNJ+ 数据手册

 浏览型号MAX32561-LNJ+的Datasheet PDF文件第2页 
ABRIDGED  
EVALUATION KIT AVAILABLE  
DATA SHEET  
MAX32561  
DeepCover Secure Arm Cortex-M3  
Flash Microcontroller  
General Description  
DeepCover embedded security solutions cloak sensitive  
Benefits and Features  
Arm Cortex M3 Processor Core Allows for Easy  
®
data under multiple layers of advanced physical security  
to provide the most secure key storage possible.  
Integration into Applications  
• 108MHz Core Operating Frequency Through PLL  
• 1MB Dual-Bank Flash Memory with Cache  
• 384KB System SRAM  
The DeepCover Secure microcontroller (MAX32561) pro-  
vides an interoperable, secure, and cost-effective solution  
to build new generations of trusted devices such as mobile  
chip and pin pads. The MAX32561 is based on an Arm®  
Cortex®-M3 processor with 1MB of embedded flash, 384KB  
of system RAM, 8KB of battery-backed AES self-encrypted  
NVSRAM. In addition to a high-performance QSPI® inter-  
face for secure code execution and data storage, it includes  
all the essential functions of mobile POS terminal including  
an RF contactless controller with the embedded transceiver,  
a cryptographic engine, a true random number generator,  
battery-backed RTC, environmental and tamper detection  
circuitry, a magnetic stripe reader, a smart card controller  
with embedded transceiver to directly support 1.8V, 3.3V,  
and 5V cards, and an integrated secure keypad controller. It  
also provides a seamless interface to monochrome graphic  
displays and includes a vast array of peripherals, SPIs,  
UARTs, DMA, and ADC that add flexibility to control and dif-  
ferentiate the system design.  
• 8KB AES Self-Encrypted NVSRAM  
Security Features Facilitate System-Level Protection  
• ISO 14443 type A/B EMV Compliant Contactless  
Reader with Internal Transceiver  
• Secure Boot Loader with Public Key Authentication  
• AES, DES and SHA Hardware Accelerators  
• Modulo Arithmetic Hardware Accelerator (MAA)  
Supporting RSA, DSA, and ECDSA  
• 9-Line Secure Keypad Controller  
• Hardware True Random-Number Generator  
• Die Shield with Dynamic Fault Detection  
• 6 External Tamper Sensors with Independent  
Random Dynamic Patterns  
• 256-Bit Flip-Flop-Based Battery-Backup AES Key  
Storage  
Temperature and Voltage Tamper Monitor  
• Real-Time Clock  
Integrated Peripherals Reduce External Component Count  
• Triple-Track Magnetic Stripe Head Interface  
• One ISO 7816 Smart Card Interface with Integrated  
Transceiver (1.8V, 3V, and 5V) and One Smart Card  
Interface Only  
Applications  
PCI Mobile Payment Terminals (mPOS)  
ATM Keyboards  
EMV Card Reader  
Contact/Contactless Pin Pads  
• USB 2.0 Device with Internal Transceiver and  
Dedicated PLL  
Functional Diagram  
2
• 2 SPI Ports, 2 UART Ports, and I C Controller  
• 6 Timers, 2 with PWM Capability  
• Up to 39 General-Purpose I/O Pins  
• 1-Channel, 10-Bit ADC  
• 4-Channel DMA Controller  
• 1 SPI Execute in Place (XiP) Master  
APB PERIPHERALS  
ARM  
NVIC  
CORTEX M3  
RTC*  
SECURITY  
MAX32561  
MPU  
MONITOR*  
I
D
S
APB BRIDGE  
WATCHDOG  
OTP  
OSC/PLL (2)  
GPIO  
APB  
AHB  
AHB  
CODE SPACE  
AHB PERIPHERALS  
FLASH  
1MB  
SRAM  
384kB  
NVSRAM  
8kB*  
TIMERS (6)  
KEYPAD  
SPI (2)  
Power Management Optimizes Battery Life and  
Reduces Active Power Consumption  
• Single 3.3V Supply Operation*  
UART (2)  
2
DMA  
USB DEVICE  
MSR  
CRYPTO  
TRNG  
ROM  
64kB  
ADC  
I
C
• Integrated Battery-Backup Switch  
• Clock Gating Function  
SMART CARD (2)  
CONTACTLESS  
SPI XiP  
128MB  
• Low-Current Battery-Backup Operation  
* BATTERY-BACKED BLOCKS  
appears at end of data sheet.  
Ordering Information  
*5V smart card support requires external 5.0V supply.  
DeepCover is a registered trademark of Maxim Integrated  
Products, Inc.  
Arm and Cortex are registered trademarks of Arm Limited (or  
its subsidiaries) in the US and/or elsewhere.  
QSPI is a trademark of Motorola, Inc.  
19-100683; Rev 1; 10/19  

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