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M74HCT161TTR PDF预览

M74HCT161TTR

更新时间: 2024-11-02 19:57:07
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
12页 97K
描述
HCT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16, TSSOP-16

M74HCT161TTR 技术参数

生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP-16针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.43计数方向:UP
系列:HCTJESD-30 代码:R-PDSO-G16
长度:5 mm负载电容(CL):50 pF
负载/预设输入:YES逻辑集成电路类型:BINARY COUNTER
最大频率@ Nom-Sup:21000000 Hz最大I(ol):0.004 A
工作模式:SYNCHRONOUS位数:4
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
电源:5 V传播延迟(tpd):54 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Counters最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
触发器类型:POSITIVE EDGE宽度:4.4 mm
最小 fmax:21 MHzBase Number Matches:1

M74HCT161TTR 数据手册

 浏览型号M74HCT161TTR的Datasheet PDF文件第2页浏览型号M74HCT161TTR的Datasheet PDF文件第3页浏览型号M74HCT161TTR的Datasheet PDF文件第4页浏览型号M74HCT161TTR的Datasheet PDF文件第5页浏览型号M74HCT161TTR的Datasheet PDF文件第6页浏览型号M74HCT161TTR的Datasheet PDF文件第7页 
M74HCT161  
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER  
HIGH SPEED :  
= 50 MHz (TYP.) at V = 4.5V  
f
MAX  
CC  
LOW POWER DISSIPATION:  
=4µA(MAX.) at T =25°C  
I
CC  
A
COMPATIBLE WITH TTL OUTPUTS :  
= 2V (MIN.) V = 0.8V (MAX)  
V
IH  
IL  
DIP  
SOP  
TSSOP  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 161  
TUBE  
T & R  
DIP  
SOP  
M74HCT161B1R  
M74HCT161M1R M74HCT161RM13TR  
M74HCT161TTR  
DESCRIPTION  
The M74HCT161 is an high speed CMOS  
TSSOP  
SYNCHRONOUS  
4-BIT  
BINARY  
PRESETTABLE COUNTER fabricated with silicon  
gate C MOS technology.  
output are provided to enable easy cascading of  
counters, which facilities easy implementation of  
N-bit counters without using external gates.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
2
The CLOCK input is active on the rising edge.  
Both LOAD and CLEAR inputs are active LOW.  
Presetting is synchronous on the rising edge of  
the clock, the function is cleared asynchronously.  
Two enable inputs (TE and PE) and CARRY  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
August 2001  
1/12  

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