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M74HCT174B1R PDF预览

M74HCT174B1R

更新时间: 2024-11-18 23:01:27
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
11页 247K
描述
HEX D-TYPE FLIP FLOP WITH CLEAR

M74HCT174B1R 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.33
系列:HCTJESD-30 代码:R-PDIP-T16
JESD-609代码:e3负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP最大I(ol):0.004 A
位数:6功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE包装方法:TUBE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
传播延迟(tpd):35 ns认证状态:Not Qualified
座面最大高度:5.1 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Matte Tin (Sn)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:7.62 mm最小 fmax:24 MHz
Base Number Matches:1

M74HCT174B1R 数据手册

 浏览型号M74HCT174B1R的Datasheet PDF文件第2页浏览型号M74HCT174B1R的Datasheet PDF文件第3页浏览型号M74HCT174B1R的Datasheet PDF文件第4页浏览型号M74HCT174B1R的Datasheet PDF文件第5页浏览型号M74HCT174B1R的Datasheet PDF文件第6页浏览型号M74HCT174B1R的Datasheet PDF文件第7页 
M54HCT174  
M74HCT174  
HEX D-TYPE FLIP FLOP WITH CLEAR  
.
.
.
.
.
.
.
HIGH SPEED  
fMAX = 56 MHz (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT TA = 25 °C  
COMPATIBLE WITH TTL OUTPUTS  
VIH = 2V (MIN.) VIL = 0.8V (MAX)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
IOH = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
PIN AND FUNCTION COMPATIBLE WITH  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
54/74LS174  
ORDER CODES :  
DESCRIPTION  
M54HCT174F1R  
M74HCT174M1R  
The M54/74HCT174 is a high speed CMOS HEX D-  
TYPEFLIP-FLOP WITH CLEAR fabricated in silicon  
gateC2MOS technology. It has the same high speed  
performance of LSTTL combined with true CMOS  
low power consumption.  
M74HCT174B1R  
M74HCT174C1R  
PIN CONNECTIONS (top view)  
Information signals applied to D inputs are transfered  
to theQ outputon thepositive goingedge oftheclock  
pulse. When the CLEAR input is held low, the Q out-  
puts are held low independently of the other inputs.  
This integrated circuit has input and output charac-  
teristics that are fully compatible with 54/74 LSTTL  
logic families. M54/74HCT devices are designed to  
directly interface HSC2MOS systems with TTL and  
NMOS components. They are also plug in replace-  
ments for LSTTL devices giving areduction of power  
consumption. All inputs are equipped with protection  
circuits against static discharge and transient excess  
voltage.  
INPUT AND OUTPUT EQUIVALENT CIRCUIT  
NC =  
No Internal  
Connection  
February 1993  
1/11  

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