Datasheet > M74HCT165

M74HCT165

更新时间： 2024-11-01 23:01:27

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		移位寄存器
页数	文件大小	规格书
13页	279K
描述
8 BIT PISO SHIFT REGISTER

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中文翻译

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数据手册

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M74HCT165 数据手册

M54HCT165

M74HCT165

8 BIT PISO SHIFT REGISTER

HIGH SPEED

_PD= 17 ns (TYP.) AT V_CC= 5 V

LOW POWER DISSIPATION

I_CC= 4 µA (MAX.) AT T_A= 25 °C

OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

BALANCED PROPAGATION DELAYS

t_PLH= t_PHL

SYMMETRICAL OUTPUT IMPEDANCE

I_OL= I_OH= 4 mA (MIN.)

B1R

(Plastic Package)

F1R

(Ceramic Package)

COMPATIBLE WITH TTL OUTPUTS

V_IH= 2 V (MIN.) V_IL= 0.8 V (MAX.)

PIN AND FUNCTION COMPATIBLE

WITH 54/74LS165

M1R

(Micro Package)

C1R

(Chip Carrier)

ORDER CODES :

M54HCT165F1R

M74HCT165B1R

M74HCT165M1R

M74HCT165C1R

DESCRIPTION

The M54/74HCT165 is a high speed CMOS 8 BIT

PISO SHIFT REGISTER fabricated in silicon gate

C²MOS technology. It has the same high speed

performance of LSTTL combined with true CMOS

low power consumption. It achives the high speed

operation similar to equivalent LSTTL while

maintaining the CMOS low power dissipation.

This device contains eight clocked master slave RS

flip-flops connected as a shift register, with auxiliary

gating to provide over-riding asynchronous parallel

entry. Parallel data entrens when the shift/loadinput

is low. The parallel data can change while shift/load

is low, provided that the recommended set-up and

hold times are observed. For clocked operation,

shift/load must be high. The two clock input perform

identically; one can be used as a clock inhibit by

applying a high signal; to permit this operation

clocking is accomplished through a 2 input nor

gates.

PIN CONNECTIONS (top view)

To avoid double clocking, however, the inhibit signal

should only go high while the clock is high.

Otherwise the rising inhibit signal will cause the

same response as rising clock edge.This integrated

circuit has input and output characteristics that are

fully compatible with 54/74 LSTTL logic families.

M54/74HCT devices are designed to directly

interface HSCMOS systems with TTL and NMOS

components. They are also plug in replacements for

LSTTL devices giving a reduction of power

consumption. All inputs are equipped with

protection circuits against static discharge and

transient excess voltage.

NC =

No Internal

Connection

October 1993

1/13

12 3 4 5 6 7...13

中文翻译

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