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M74HC353TTR PDF预览

M74HC353TTR

更新时间: 2024-11-21 20:54:47
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
11页 187K
描述
HC/UH SERIES, DUAL 4 LINE TO 1 LINE MULTIPLEXER, INVERTED OUTPUT, PDSO16, TSSOP-16

M74HC353TTR 技术参数

生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP16,.25针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.78系列:HC/UH
JESD-30 代码:R-PDSO-G16长度:5 mm
负载电容(CL):50 pF逻辑集成电路类型:MULTIPLEXER
最大I(ol):0.004 A功能数量:2
输入次数:4输出次数:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL电源:2/6 V
Prop。Delay @ Nom-Sup:45 ns传播延迟(tpd):95 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Multiplexer/Demultiplexers最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
宽度:4.4 mmBase Number Matches:1

M74HC353TTR 数据手册

 浏览型号M74HC353TTR的Datasheet PDF文件第2页浏览型号M74HC353TTR的Datasheet PDF文件第3页浏览型号M74HC353TTR的Datasheet PDF文件第4页浏览型号M74HC353TTR的Datasheet PDF文件第5页浏览型号M74HC353TTR的Datasheet PDF文件第6页浏览型号M74HC353TTR的Datasheet PDF文件第7页 
M74HC353  
DUAL 4 CHANNEL MULTIPLEXER  
WITH 3 STATE OUTPUT (INVERTING)  
HIGH SPEED:  
= 18ns (TYP.) at V = 6V  
t
PD  
CC  
LOW POWER DISSIPATION:  
= 4µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
TUBE  
V
CC  
DIP  
SOP  
M74HC353B1R  
M74HC353M1R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 353  
M74HC353RM13TR  
M74HC353TTR  
TSSOP  
DESCRIPTION  
The M74HC353 is an high speed CMOS DUAL 4  
CHANNEL MULTIPLEXER fabricated with silicon  
gate C MOS technology.  
(G) can be used to inhibit the data output; the  
output of M74HC353 is at high impedance,  
unconditionally.  
2
Each of these data (1C0-1C3, 2C0-2C3) is  
selected by the two address inputs A and B.  
Separate strobe inputs (1G, 2G) are provided for  
each of the two four-line sections. The strobe input  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
July 2001  
1/11  

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WITH LATCHES 3-STATE 8 CHANNEL MULTIPLEXER/REGISTER