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M74HC356M1R PDF预览

M74HC356M1R

更新时间: 2024-11-20 22:39:59
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 复用器锁存器
页数 文件大小 规格书
12页 273K
描述
WITH LATCHES 3-STATE 8 CHANNEL MULTIPLEXER/REGISTER

M74HC356M1R 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP20,.4针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.56其他特性:TRANSPARENT ADDRESS LATCHES; 3 ENABLE INPUTS; REGISTERED DATA INPUTS
系列:HC/UHJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:12.8 mm
负载电容(CL):50 pF逻辑集成电路类型:MULTIPLEXER
最大I(ol):0.006 A功能数量:1
输入次数:8输出次数:1
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/6 V
Prop。Delay @ Nom-Sup:78 ns传播延迟(tpd):420 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:Multiplexer/Demultiplexers最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmBase Number Matches:1

M74HC356M1R 数据手册

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M54HC356  
M74HC356  
8 CHANNEL MULTIPLEXER/REGISTER  
WITH LATCHES (3-STATE)  
.
.
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HIGH SPEED  
tPD = 25 ns (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
15 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
|IOH| = IOL = 6 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE WITH  
54/74LS356  
ORDER CODES :  
M54HC356F1R  
M74HC356B1R  
M74HC356M1R  
M74HC356C1R  
PIN CONNECTIONS (top view)  
DESCRIPTION  
The M54/74HC356 is a high speed CMOS8-CHAN-  
NEL MULTIPLEXER/REGISTER (3-State) fabri-  
cated in silicon gate C2MOS technology. It has the  
same high speed performance of LSTTL combined  
with true CMOS low consumption.  
This device contains an 8channel digital multiplexer  
with an 8-bit input data register and a 3-bit address  
input register with 3-state outputs. The one of eight  
input data will be provided on the Y output pin (non-  
inverted output) and W output pin (inverted output)  
is determineted by the address data.  
The information at the data inputs (D0 to D7) is  
stored in the 8-bit flip-flop at the positive going edge  
of clock input (CLOCK). The information at the ad-  
dress inputs (S0 to S2) is stored in the 3-bit latch at  
the negative pulse on SC input. These outputs are  
disabled to be high-impedance when input G1 is  
held high, input G2 is held high or input G3 is held  
low. This device is suitable for interfacing with bus  
linesin a bus organized system. The M54/74HC356  
is similar in function tothe M54/74HC354, which has  
an 8-bit latch as the data register instead of an 8-bit  
flip-flop. All inputs are equipped with protection cir-  
cuits against static discharge and transient excess  
voltage.  
NC =  
No Internal  
Connection  
January 1993  
1/12  

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