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M74HC354M1R PDF预览

M74HC354M1R

更新时间: 2024-11-24 22:36:15
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 解复用器逻辑集成电路光电二极管输入元件双倍数据速率
页数 文件大小 规格书
12页 266K
描述
8 CHANNEL MULTIPLEXER/REGISTER 3 STATE

M74HC354M1R 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP-20针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.79Is Samacsys:N
其他特性:TRANSPARENT ADDRESS/DATA LATCHES; 3 ENABLE INPUTS系列:HC/UH
JESD-30 代码:R-PDSO-G20JESD-609代码:e4
长度:12.8 mm负载电容(CL):50 pF
逻辑集成电路类型:MULTIPLEXER最大I(ol):0.006 A
功能数量:1输入次数:8
输出次数:1端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 VProp。Delay @ Nom-Sup:63 ns
传播延迟(tpd):375 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:Multiplexer/Demultiplexers
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):4.5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5 mm
Base Number Matches:1

M74HC354M1R 数据手册

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M54HC354  
M74HC354  
8 CHANNEL MULTIPLEXER/REGISTER (3 STATE)  
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HIGH SPEED  
tPD = 24 ns (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
15 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
|IOH| = IOL = 6 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS354  
ORDER CODES :  
M54HC354F1R  
M74HC354B1R  
M74HC354M1R  
M74HC354C1R  
PIN CONNECTIONS (top view)  
DESCRIPTION  
The M54/74HC354 is a high speed CMOS8-CHAN-  
NEL MULTIPLEXER/REGISTER (3-state) fabri-  
cated in silicon gate C2MOS technology. It has the  
same high speed performance of LSTTL combined  
with true CMOS low consumption.  
This device contains an 8channel digital multiplexer  
with an 8-bit input data register and a 3-bit address  
input register with 3-state outputs. The one of eight  
input data will be provided on the Y output pin (non-  
inverted output) and W output pin (inverted output)  
determined by the address data.  
The information at the data inputs (D0 to D7) is  
stored in the 8-bit latch at the negative pulse on DC  
input. The information at the address inputs (S0 to  
S2) is stored in the 3-bit latch at the negative pulse  
on SC input. These outputs are disabled to be high-  
impedance when input G1 is held high, input G2 is  
held high or input G3 is held low. This device is suit-  
able for interfacing with bus lines in a bus organized  
system.  
The M54/74HC354 is similar in function to the  
M54/74HC356, which has an 8-bit flip-flop as the  
data register instead of an 8-bit latch. All inputs are  
equipped with protection circuits against static dis-  
charge and transient excess voltage.  
NC =  
No Internal  
Connection  
April 1993  
1/12  

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