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M74HC259C1R PDF预览

M74HC259C1R

更新时间： 2024-11-01 22:57:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器锁存器逻辑集成电路双倍数据速率
页数 文件大小 规格书
12页 266K
描述
8 BIT ADDRESSABLE LATCH

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中文翻译

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M74HC259C1R 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QLCC包装说明：PLASTIC, LCC-20
针数：20Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.71
Is Samacsys：N其他特性：1:8 DMUX FOLLOWED BY LATCH; RESET ACTIVE ONLY WHEN LATCH ENABLE IS HIGH
系列：HC/UHJESD-30 代码：S-PQCC-J20
JESD-609代码：e3长度：8.9662 mm
负载电容（CL）：50 pF逻辑集成电路类型：D LATCH
最大I（ol）：0.004 A位数：1
功能数量：1端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC20,.4SQ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2/6 V
Prop。Delay @ Nom-Sup：48 ns传播延迟（tpd）：38 ns
认证状态：Not Qualified座面最大高度：4.57 mm
子类别：FF/Latches最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：LOW LEVEL宽度：8.9662 mm
Base Number Matches：1

M74HC259C1R 数据手册

 浏览型号M74HC259C1R的Datasheet PDF文件第2页浏览型号M74HC259C1R的Datasheet PDF文件第3页浏览型号M74HC259C1R的Datasheet PDF文件第4页浏览型号M74HC259C1R的Datasheet PDF文件第5页浏览型号M74HC259C1R的Datasheet PDF文件第6页浏览型号M74HC259C1R的Datasheet PDF文件第7页 
M54HC259  
M74HC259  
8 BIT ADDRESSABLE LATCH  
.
.
.
.
.
.
.
.
HIGH SPEED  
tPD = 15 ns (TYP.) at VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) at TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL PROPAGATION DELAYS  
IOH = IOL = 4 mA (MIN.)  
BALANCED PRORAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
VCC (OPR) = 2 V to 6 V  
PIN AND FUNCTION COMPATIBLE WITH  
54/74LS259  
ORDER CODES :  
M54HC259F1R  
M74HC259B1R  
M74HC259M1R  
M74HC259C1R  
DESCRIPTION  
The M54/74HC259 is a high speed CMOS 8 BIT  
ADDRESSABLE LATCH fabricated in silicon gate  
C2MOS technology. It has the same highspeed per-  
formance of LSTTL combined with true CMOS low  
power consumption.  
PIN CONNECTIONS (top view)  
The M54HC259/M74HC259 has single data input  
(D) 8 latch outputs (Q0-Q7), 3 address inputs (A, B,  
and C), common enable input (E), and a common  
CLEAR input. To operate this device as an address-  
able latch, data is held on the D input, and the ad-  
dressof the latch into which the data isto beentered  
is held on the A, B, and C inputs. When ENABLE is  
taken low the data flows through to the addresses  
output. The data is stored on the positive-going  
edge of the ENABLE pulse. Allunaddressed latches  
will remain unaffected. With ENABLE in the high  
state the device is deselected and all latches remain  
in their previous state, unaffected by changes onthe  
data or address inputs. To eliminate the possibility  
of entering erroneous data into the latches, the EN-  
ABLE should be held high (inactive) while the ad-  
dresslines are changing. IfENABLE isheld highand  
CLEAR is taken low all eight latches are cleared to  
the low state. IfENABLE islowall latches except the  
addressed latch will be cleared. The addressed  
latch will instead follow the Dinput, effectively imple-  
menting a 3-to 8 line decoder.  
NC =  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
No Internal  
Connection  
October 1992  
1/12  
1234567...12

中文翻译

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