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M74HC279 PDF预览

M74HC279

更新时间: 2024-11-01 22:57:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
10页 241K
描述
QUAD S - R LATCH

M74HC279 数据手册

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M54HC279  
M74HC279  
QUAD S - R LATCH  
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HIGH SPEED  
tPD = 12 ns (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 2 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
IOH = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS279  
ORDER CODES :  
M54HC279F1R  
M74HC279B1R  
M74HC279M1R  
M74HC279C1R  
PIN CONNECTIONS (top view)  
DESCRIPTION  
The M54/74HC279 isa high speed CMOS QUAD S  
- R LATCH fabricated in silicon gate C2MOS tech-  
nology. It has the same high speed performance of  
LSTTL combined with true CMOS low power con-  
sumption.  
All inputs are equipped with protection circuits  
against static discharge and transient excess volt-  
age.  
INPUT AND OUTPUT EQUIVALENT CIRCUIT  
NC =  
No Internal  
Connection  
March 1993  
1/10  

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