Datasheet > M74HC280TTR

M74HC280TTR

更新时间： 2024-11-25 05:00:55

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		/
页数	文件大小	规格书
9页	304K
描述
9 BIT PARITY GENERATOR

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中文翻译

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数据手册

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M74HC280TTR 数据手册

M74HC280

9 BIT PARITY GENERATOR

■

HIGH SPEED :

= 22ns (TYP.) at V = 6V

LOW POWER DISSIPATION:

=4µA(MAX.) at T =25°C

HIGH NOISE IMMUNITY:

= V = 28 % V (MIN.)

NIH

NIL

DIP

SOP

TSSOP

T & R

SYMMETRICAL OUTPUT IMPEDANCE:

|I | = I = 4mA (MIN)

BALANCED PROPAGATION DELAYS:

ORDER CODES

PACKAGE

PLH

PHL

WIDE OPERATING VOLTAGE RANGE:

(OPR) = 2V to 6V

TUBE

DIP

SOP

M74HC280B1R

M74HC280M1R

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 280

M74HC280RM13TR

M74HC280TTR

TSSOP

DESCRIPTION

The M74HC280 is an high speed CMOS 9-BIT

PARITY GENERATOR fabricated with silicon gate

C MOS technology.

It is composed of nine data inputs (A to I) and odd/

even parity outputs (ΣODD and ΣEVEN). The nine

data inputs control the output conditions. When

the number of high level input is odd, ΣODD

output is kept high and ΣEVEN output low.

Conversely, when the output is even, ΣEVEN

output is kept high and ΣODD low.

The IC generates either odd or even parity making

it flexible application. The word-length capability is

easily expanded by cascading.

All inputs are equipped with protection circuits

against static discharge and transient excess

voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

July 2001

1/9

12 3 4 5 6 7...9

中文翻译

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