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M74HC259TTR PDF预览

M74HC259TTR

更新时间： 2024-11-02 03:15:39
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器锁存器逻辑集成电路光电二极管双倍数据速率
页数 文件大小 规格书
13页 558K
描述
8 BIT ADDRESSABLE LATCH

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中文翻译

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M74HC259TTR 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP16,.25
针数：16Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.71
Is Samacsys：N系列：HC/UH
JESD-30 代码：R-PDSO-G16JESD-609代码：e4
长度：5 mm负载电容（CL）：50 pF
逻辑集成电路类型：D LATCH最大I（ol）：0.004 A
位数：8功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：260电源：2/6 V
Prop。Delay @ Nom-Sup：57 ns传播延迟（tpd）：210 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：FF/Latch最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：4.5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
触发器类型：LOW LEVEL宽度：4.4 mm
Base Number Matches：1

M74HC259TTR 数据手册

 浏览型号M74HC259TTR的Datasheet PDF文件第2页浏览型号M74HC259TTR的Datasheet PDF文件第3页浏览型号M74HC259TTR的Datasheet PDF文件第4页浏览型号M74HC259TTR的Datasheet PDF文件第5页浏览型号M74HC259TTR的Datasheet PDF文件第6页浏览型号M74HC259TTR的Datasheet PDF文件第7页 
M74HC259  
8 BIT ADDRESSABLE LATCH  
■
■
■
■
■
■
■
HIGH SPEED :  
= 20 ns (TYP.) at V = 6V  
t
PD  
CC  
LOW POWER DISSIPATION:  
=4µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
TUBE  
V
CC  
DIP  
SOP  
M74HC259B1R  
M74HC259M1R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 259  
M74HC259RM13TR  
M74HC259TTR  
TSSOP  
DESCRIPTION  
The M74HC259 is an high speed CMOS 8 BIT  
ADDRESSABLE LATCH fabricated with silicon  
gate C MOS technology.  
latches remain in their previous state, unaffected  
by changes on the data or address inputs. To  
eliminate the possibility of entering erroneous data  
into the latches, the ENABLE should be held high  
(inactive) while the address lines are changing. If  
ENABLE is held high and CLEAR is taken low all  
eight latches are cleared to the low state. If  
ENABLE is low all latches except the addressed  
latch will be cleared. The addressed latch will  
2
The M74HC259 has single data input (D) 8 latch  
outputs (Q0-Q7), 3 address inputs (A, B, and C),  
common enable input (E), and a common CLEAR  
input. To operate this device as an addressable  
latch, data is held on the D input, and the address  
of the latch into which the data is to be entered is  
held on the A, B, and C inputs. When ENABLE is  
taken low the data flows through to the addresses  
output. The data is stored on the positive-going  
edge of the ENABLE pulse. All unaddressed  
latches will remain unaffected. With ENABLE in  
the high state the device is deselected and all  
instead follow the  
D
input, effectively  
implementing a 3-to-8 line decoder.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
July 2001  
1/13  
1234567...13

中文翻译

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