M74HC259YTTR

更新时间： 2024-11-03 17:33:19

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		锁存器
页数	文件大小	规格书
12页	266K
描述
8位可寻址锁存器

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中文翻译

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数据手册

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M74HC259YTTR 数据手册

M54HC259

M74HC259

8 BIT ADDRESSABLE LATCH

HIGH SPEED

t_PD= 15 ns (TYP.) at V_CC= 5 V

LOW POWER DISSIPATION

I_CC= 4 µA (MAX.) at T_A= 25 °C

HIGH NOISE IMMUNITY

V_NIH= V_NIL= 28 % V_CC(MIN.)

OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

SYMMETRICAL PROPAGATION DELAYS

IOH = I_OL= 4 mA (MIN.)

BALANCED PRORAGATION DELAYS

t_PLH= t_PHL

WIDE OPERATING VOLTAGE RANGE

B1R

(Plastic Package)

F1R

(Ceramic Package)

M1R

(Micro Package)

C1R

(Chip Carrier)

V_CC(OPR) = 2 V to 6 V

PIN AND FUNCTION COMPATIBLE WITH

54/74LS259

ORDER CODES :

M54HC259F1R

M74HC259B1R

M74HC259M1R

M74HC259C1R

DESCRIPTION

The M54/74HC259 is a high speed CMOS 8 BIT

ADDRESSABLE LATCH fabricated in silicon gate

C²MOS technology. It has the same highspeed per-

formance of LSTTL combined with true CMOS low

power consumption.

PIN CONNECTIONS (top view)

The M54HC259/M74HC259 has single data input

(D) 8 latch outputs (Q0-Q7), 3 address inputs (A, B,

and C), common enable input (E), and a common

CLEAR input. To operate this device as an address-

able latch, data is held on the D input, and the ad-

dressof the latch into which the data isto beentered

is held on the A, B, and C inputs. When ENABLE is

taken low the data flows through to the addresses

output. The data is stored on the positive-going

edge of the ENABLE pulse. Allunaddressed latches

will remain unaffected. With ENABLE in the high

state the device is deselected and all latches remain

in their previous state, unaffected by changes onthe

data or address inputs. To eliminate the possibility

of entering erroneous data into the latches, the EN-

ABLE should be held high (inactive) while the ad-

dresslines are changing. IfENABLE isheld highand

CLEAR is taken low all eight latches are cleared to

the low state. IfENABLE islowall latches except the

addressed latch will be cleared. The addressed

latch will instead follow the Dinput, effectively imple-

menting a 3-to 8 line decoder.

NC =

All inputs are equipped with protection circuits

against static discharge and transient excess

voltage.

No Internal

Connection

October 1992

1/12

12 3 4 5 6 7...12

中文翻译

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与M74HC259YTTR相关器件

型号	品牌	获取价格	描述	数据表
M74HC266	STMICROELECTRONICS	获取价格	HC266 QUAD EXCLUSIVE NOR GATE WITH OPEN DRAIN HC7266 QUAD EXCLUSIVE NOR GATE
M74HC266ADP	MITSUBISHI	获取价格	XNOR Gate, CMOS, PDSO14
M74HC266AFP	MITSUBISHI	获取价格	XNOR Gate, CMOS, PDSO14
M74HC266AP	MITSUBISHI	获取价格	XNOR Gate, CMOS, PDIP14
M74HC266B1R	STMICROELECTRONICS	获取价格	HC266 QUAD EXCLUSIVE NOR GATE WITH OPEN DRAIN HC7266 QUAD EXCLUSIVE NOR GATE
M74HC266C1R	STMICROELECTRONICS	获取价格	HC266 QUAD EXCLUSIVE NOR GATE WITH OPEN DRAIN HC7266 QUAD EXCLUSIVE NOR GATE
M74HC266F1	STMICROELECTRONICS	获取价格	IC,LOGIC GATE,QUAD 2-INPUT XNOR,HC-CMOS,DIP,14PIN,CERAMIC
M74HC266F1R	STMICROELECTRONICS	获取价格	HC266 QUAD EXCLUSIVE NOR GATE WITH OPEN DRAIN HC7266 QUAD EXCLUSIVE NOR GATE
M74HC266M1R	STMICROELECTRONICS	获取价格	HC266 QUAD EXCLUSIVE NOR GATE WITH OPEN DRAIN HC7266 QUAD EXCLUSIVE NOR GATE
M74HC266P	MITSUBISHI	获取价格	XNOR Gate, CMOS, PDIP14

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