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M66280FP PDF预览

M66280FP

更新时间: 2024-01-26 00:20:37
品牌 Logo 应用领域
三菱 - MITSUBISHI 存储光电二极管先进先出芯片
页数 文件大小 规格书
12页 114K
描述
5120 x 8-BIT LINE MEMORY

M66280FP 技术参数

生命周期:Obsolete零件包装代码:SSOP
包装说明:5.30 X 10.10 MM, 0.80 MM PITCH, PLASTIC, SSOP-24针数:24
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.7
Is Samacsys:N最长访问时间:18 ns
其他特性:LINE MEMORY周期时间:25 ns
JESD-30 代码:R-PDSO-G24长度:10.1 mm
内存密度:40960 bit内存宽度:8
功能数量:1端子数量:24
字数:5120 words字数代码:5000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:5KX8
可输出:NO封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SOP24,.3,32
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
并行/串行:PARALLEL电源:3.15 V
认证状态:Not Qualified座面最大高度:2.1 mm
子类别:Other Memory ICs最大压摆率:0.07 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3.15 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUAL宽度:5.3 mm
Base Number Matches:1

M66280FP 数据手册

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MITSUBISHI <DIGITAL ASSP>  
M66280FP  
5120 x 8-BIT LINE MEMORY  
DESCRIPTION  
PIN CONFIGURATION (TOP VIEW)  
The M66280FP is high speed line memory that uses high  
performance silicon gate CMOS process technology and adopts  
the FIFO (First In First Out) structure consisting of 5120 words x 8  
bits.  
The M66280FP, performing reading and writing operations at  
different cycles independently and asynchronously, is optimal for  
buffer memory to be used between equipment of different data  
processing speeds.  
Q0  
Q1  
1
2
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
D0  
D1  
DATA INPUT  
DATA OUTPUT  
Q2  
D2  
3
Q3  
D3  
4
FEATURES  
READ ENABLE  
INPUT  
READ RESET  
INPUT  
WRITE ENABLE  
INPUT  
WRITE RESET  
INPUT  
REB  
• Memory configuration  
• High speed cycle  
• High speed access  
• Output hold  
5120 words x 8 bits (dynamic memory)  
25 ns (Min.)  
18 ns (Max.)  
WEB  
WRESB  
5
RRESB  
GND  
RCK  
Q4  
6
VCC  
WCK  
D4  
7
3 ns (Min.)  
READ CLOCK  
INPUT  
• Reading and writing operations can be completely carried out  
independently and asynchronously.  
• Variable length delay bit  
WRITE CLOCK  
INPUT  
8
9
• Input/output  
• Output  
TTL direct connection allowable  
3 states  
Q5  
D5  
10  
11  
12  
DATA OUTPUT  
DATA INPUT  
Q6  
Q7  
D6  
D7  
APPLICATION  
• Digital copying machine  
,
laser beam printer, high speed facsimile,  
etc.  
Outline 24P2Q-A(SSOP)  
FUNCTION  
When write enable input WEB is set to "L", the contents of data  
inputs D0 to D7 are read in synchronization with a rising edge of  
write lock input WCK to perform writing operation. When this is the  
case,the write address counter is also incremented simultaneously.  
When WEB is set to "H", the writing operation is inhibited and the  
write address counter stops.  
When write reset input WRESB is set to "L", the write address  
counter is initialized.  
When read enable input REB is set to "L", the contents of memory  
are output to data outputs Q0 to Q7 in synchronization with a rising  
edge of read clock input RCK to perform reading operation. When  
this is the case, the read address counter is incremented  
simultaneously.  
When REB is set to "H", the reading operation is inhibited and the  
read address counter stops. The outputs are placed in a high  
impedance state.  
When read reset input RRESB is set to "L", the read address  
counter is initialized.  
1

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