M66287FP

更新时间： 2024-02-19 23:10:08

品牌	Logo	应用领域
三菱 - MITSUBISHI		存储内存集成电路
页数	文件大小	规格书
21页	190K
描述
262144-word x 8-bit x 3-FIELD MEMORY

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M66287FP 技术参数

生命周期：	Transferred	零件包装代码：	QFP
包装说明：	LFQFP,	针数：	100
Reach Compliance Code：	compliant	HTS代码：	8542.32.00.71
风险等级：	5.28	Is Samacsys：	N
JESD-30 代码：	S-PQFP-G100	长度：	14 mm
内存密度：	6291456 bit	内存集成电路类型：	MEMORY CIRCUIT
内存宽度：	8	功能数量：	1
端子数量：	100	字数：	786432 words
字数代码：	768000	工作模式：	ASYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	768KX8	封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH	认证状态：	Not Qualified
座面最大高度：	1.7 mm	最大供电电压 (Vsup)：	1.98 V
最小供电电压 (Vsup)：	1.62 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
宽度：	14 mm	Base Number Matches：	1

M66287FP 数据手册

MITSUBISHI <DIGITAL ASSP>

M66287FP

262144-word x 8-bit x 3-FIELD MEMORY

DESCRIPTION

The M66287FP is a high-speed field memory with three FIFO (First In First Out) memories of 262144-word x 8-bit

configuration (2M bits) which uses high-performance silicon gate CMOS process technology. One of three FIFO memories

consists of two FIFO memories of 262144-word x 4-bit (1M bits). Five types of operation can be performed through the

following mode settings:

Mode1 : 3-system delay data output by 3-system individual input of 256K-word x 8-bit FIFO

Mode2 : Simultaneous output of 1 to 3-line delay data by 1-system input of 256K-word x 8-bit FIFO

Mode3 : Simultaneous output of 1 to 2-line delay data by 1-system input of 256K-word x 8-bit FIFO

and,1-system delay data output by 1-system input of 256K-word x 8-bit FIFO

Mode4 : 2-system delay data output by 2-system individual input of 256K-word x 12-bit FIFO

Mode5 : Simultaneous output of 1 to 2-line delay data by 1-system input of 256K-word x 12-bit FIFO

The above-mentioned function is most suitable for image data correction across multiple fields. Because three pieces of

2M-bit FIFO are contained in one chip, a low power consumption of a set can be realized.

FEATURES

z Memory configuration

The total memory capacity is 6M bits (static memory).

The following two types of memory configurations can be selected.

262144-word x 8-bit x 3-line configuration

262144-word x 12-bit x 2-line configuration

16.6 ns (Min.)

z High - speed cycle

z High - speed access

z Output hold

13.0 ns (Max.)

2.0 ns (Min.)

z Supply voltage

Internal = 1.8 V ± 0.18 V

I/O = 3.3 V ± 0.3 V

z Variable length delay bit

z Five modes can be selected

z Write and read function can be operated completely independently and asynchronously

z Output

3 states

z Package

100pin QFP (100P6Q-A)

APPLICATION

W-CDMA base station, Digital PPC, Digital television, VTR and so on.

MODE DESCRIPTIONS DRAWING

2M-bit x 3 configuration

8-bit bus I/F

3M-bit x 2 configuration

12-bit bus I/F

MODE 1

MODE 2

MODE 3

MODE 4

MODE 5

DA<7:0>

WCKA

WRESA

WEA

QA<7:0>

RCKA

DA<7:0>

WCKA

QA<7:0>

RCKA

DA<11:0>

WCKA

DA<7:0>

WCKA

WRESA

WEA

QA<7:0>

RCKA

QA<11:0>

DA<11:0>

QA<11:0>

256K

8-bit

FIFO

256K

8-bit

FIFO

256K

12-bit

FIFO

256K

12-bit

FIFO

RCKA

WCKA

WRESA

RRESA

8-bit

FIFO

RRESA

REA

RRESA

WRESA

WEA

RRESA

REA

RRESA

REA

WEA

REA

WEA

DB<7:0>

WCKB

WRESB

WEB

QB<7:0>

RCKB

256K

8-bit

FIFO

256K

8-bit

FIFO

QB<7:0>

8-bit

FIFO

RRESB

REB

DB<11:0>

WCKB

QB<11:0>

RCKB

12 256K

12-bit

FIFO

256K

12-bit

FIFO

QB<11:0>

WRESB

WEB

RRESB

REB

QC<7:0>

DC<7:0>

WCKC

WRESC

WEC

QC<7:0>

RCKC

DC<7:0>

WCKC

WRESC

WEC

256K

8-bit

FIFO

256K

8-bit

FIFO

256K

8-bit

FIFO

RCKC

RRESC

REC

QC<7:0>

RRESC

REC

The three pieces of 256K- The three pieces of 256K- The two pieces of 256K-

The two pieces of 256K-

word x 8-bit FIFO can be

operated completely

independently.

word x 8-bit FIFO are

cascade-connected.

Write and read operation

of FIFO after the 2nd line

is controlled by the read

system pin of the 1st line.

word x 8-bit FIFO are

word x 12-bit FIFO can be word x 12-bit FIFO are

cascade-connected and, a operated completely

piece of 256K-word x 8-bit independently.

FIFO can be operated

completely independently.

Write and read operation

cascade-connected.

Write and read operation

of FIFO at the 2nd line is

controlled by the read

system pin of the 1st line.

of FIFO at the 2nd line is

controlled by the read

system pin of the 1st line.

Note: Please refer to “Pin Assignment Table” in “MODE 4 and MODE 5 OPERATION DESCRIPTIONS” for

assignment of external pins, Dx<11:0> and Qx<11:0> when used in 12-bit bus interface.

12 3 4 5 6 7...21

中文翻译

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与M66287FP相关器件

型号	品牌	获取价格	描述	数据表
M66-288	MICRO-ELECTRONICS	获取价格	Tone/Music Synthesizer, PBCY3, TO-92
M66288FP	RENESAS	获取价格	262144-word x 8-bit x 3-FIFO MEMORY
M66-289	MICRO-ELECTRONICS	获取价格	Tone/Music Synthesizer, PBCY3, TO-92
M66290AFP	RENESAS	获取价格	USB DEVICE CONTROLLER
M66290AFP	MITSUBISHI	获取价格	USB DEVICE CONTROLLER
M66290AGP	MITSUBISHI	获取价格	USB DEVICE CONTROLLER
M66290AGP	RENESAS	获取价格	USB DEVICE CONTROLLER
M66-291	MICRO-ELECTRONICS	获取价格	Tone/Music Synthesizer, PBCY3, TO-92
M66291GP	RENESAS	获取价格	ASSP (USB2.0 Device Controller)
M66291HP	RENESAS	获取价格	ASSP (USB2.0 Device Controller)

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