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M66287FP

更新时间： 2024-11-20 22:46:35
品牌 Logo 应用领域
三菱 - MITSUBISHI 存储内存集成电路
页数 文件大小 规格书
21页 190K
描述
262144-word x 8-bit x 3-FIELD MEMORY

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中文翻译

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M66287FP 技术参数

是否Rohs认证：不符合生命周期：Transferred
零件包装代码：QFP包装说明：LFQFP, QFP100,.63SQ,20
针数：100Reach Compliance Code：unknown
HTS代码：8542.32.00.71风险等级：5.29
Is Samacsys：N最长访问时间：13 ns
JESD-30 代码：S-PQFP-G100JESD-609代码：e0
长度：14 mm内存密度：6291456 bit
内存集成电路类型：MEMORY CIRCUIT内存宽度：8
功能数量：1端子数量：100
字数：786432 words字数代码：768000
工作模式：ASYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：768KX8
封装主体材料：PLASTIC/EPOXY封装代码：LFQFP
封装等效代码：QFP100,.63SQ,20封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH电源：1.8,3.3 V
认证状态：Not Qualified座面最大高度：1.7 mm
最大待机电流：0.145 A子类别：Other Memory ICs
最大压摆率：0.145 mA最大供电电压 (Vsup)：1.98 V
最小供电电压 (Vsup)：1.62 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD宽度：14 mm
Base Number Matches：1

M66287FP 数据手册

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MITSUBISHI <DIGITAL ASSP>  
M66287FP  
262144-word x 8-bit x 3-FIELD MEMORY  
DESCRIPTION  
The M66287FP is a high-speed field memory with three FIFO (First In First Out) memories of 262144-word x 8-bit  
configuration (2M bits) which uses high-performance silicon gate CMOS process technology. One of three FIFO memories  
consists of two FIFO memories of 262144-word x 4-bit (1M bits). Five types of operation can be performed through the  
following mode settings:  
Mode1 : 3-system delay data output by 3-system individual input of 256K-word x 8-bit FIFO  
Mode2 : Simultaneous output of 1 to 3-line delay data by 1-system input of 256K-word x 8-bit FIFO  
Mode3 : Simultaneous output of 1 to 2-line delay data by 1-system input of 256K-word x 8-bit FIFO  
and,1-system delay data output by 1-system input of 256K-word x 8-bit FIFO  
Mode4 : 2-system delay data output by 2-system individual input of 256K-word x 12-bit FIFO  
Mode5 : Simultaneous output of 1 to 2-line delay data by 1-system input of 256K-word x 12-bit FIFO  
The above-mentioned function is most suitable for image data correction across multiple fields. Because three pieces of  
2M-bit FIFO are contained in one chip, a low power consumption of a set can be realized.  
FEATURES  
z Memory configuration  
The total memory capacity is 6M bits (static memory).  
The following two types of memory configurations can be selected.  
262144-word x 8-bit x 3-line configuration  
262144-word x 12-bit x 2-line configuration  
16.6 ns (Min.)  
z High - speed cycle  
z High - speed access  
z Output hold  
13.0 ns (Max.)  
2.0 ns (Min.)  
z Supply voltage  
Internal = 1.8 V ± 0.18 V  
I/O = 3.3 V ± 0.3 V  
z Variable length delay bit  
z Five modes can be selected  
z Write and read function can be operated completely independently and asynchronously  
z Output  
3 states  
z Package  
100pin QFP (100P6Q-A)  
APPLICATION  
W-CDMA base station, Digital PPC, Digital television, VTR and so on.  
MODE DESCRIPTIONS DRAWING  
2M-bit x 3 configuration  
8-bit bus I/F  
3M-bit x 2 configuration  
12-bit bus I/F  
MODE 1  
MODE 2  
MODE 3  
MODE 4  
MODE 5  
12  
12  
8
8
8
8
8
8
8
8
12  
12  
DA<7:0>  
WCKA  
WRESA  
WEA  
QA<7:0>  
RCKA  
DA<7:0>  
WCKA  
QA<7:0>  
RCKA  
DA<11:0>  
WCKA  
DA<7:0>  
WCKA  
WRESA  
WEA  
QA<7:0>  
RCKA  
QA<11:0>  
DA<11:0>  
QA<11:0>  
256K  
x
8-bit  
FIFO  
256K  
x
8-bit  
FIFO  
256K  
x
256K  
x
12-bit  
FIFO  
256K  
x
12-bit  
FIFO  
RCKA  
RCKA  
WCKA  
WRESA  
RRESA  
8-bit  
FIFO  
RRESA  
REA  
RRESA  
WRESA  
WRESA  
WEA  
RRESA  
REA  
RRESA  
REA  
REA  
WEA  
REA  
WEA  
8
DB<7:0>  
WCKB  
WRESB  
WEB  
QB<7:0>  
RCKB  
256K  
x
256K  
x
8-bit  
FIFO  
256K  
x
8-bit  
FIFO  
8
8
8
8
8
QB<7:0>  
QB<7:0>  
8-bit  
FIFO  
RRESB  
REB  
12  
12  
DB<11:0>  
WCKB  
QB<11:0>  
RCKB  
12 256K  
x
12-bit  
FIFO  
12  
256K  
x
12-bit  
FIFO  
QB<11:0>  
8
8
8
WRESB  
WEB  
RRESB  
REB  
QC<7:0>  
DC<7:0>  
WCKC  
WRESC  
WEC  
QC<7:0>  
RCKC  
DC<7:0>  
WCKC  
WRESC  
WEC  
256K  
x
8-bit  
FIFO  
256K  
x
8-bit  
FIFO  
256K  
x
8-bit  
FIFO  
8
RCKC  
RRESC  
REC  
QC<7:0>  
RRESC  
REC  
The three pieces of 256K- The three pieces of 256K- The two pieces of 256K-  
The two pieces of 256K-  
The two pieces of 256K-  
word x 8-bit FIFO can be  
operated completely  
independently.  
word x 8-bit FIFO are  
cascade-connected.  
Write and read operation  
of FIFO after the 2nd line  
is controlled by the read  
system pin of the 1st line.  
word x 8-bit FIFO are  
word x 12-bit FIFO can be word x 12-bit FIFO are  
cascade-connected and, a operated completely  
piece of 256K-word x 8-bit independently.  
FIFO can be operated  
completely independently.  
Write and read operation  
cascade-connected.  
Write and read operation  
of FIFO at the 2nd line is  
controlled by the read  
system pin of the 1st line.  
of FIFO at the 2nd line is  
controlled by the read  
system pin of the 1st line.  
Note: Please refer to “Pin Assignment Table” in “MODE 4 and MODE 5 OPERATION DESCRIPTIONS” for  
assignment of external pins, Dx<11:0> and Qx<11:0> when used in 12-bit bus interface.  
© 2002 MITSUBISHI ELECTRIC CORPORATION  
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中文翻译

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