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M66281FP PDF预览

M66281FP

更新时间: 2024-11-21 05:47:19
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
16页 176K
描述
5120 × 8-Bit × 2 Line Memory

M66281FP 数据手册

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M66281FP  
5120 × 8-Bit × 2 Line Memory  
REJ03F0254-0200  
Rev.2.00  
Sep 14, 2007  
Description  
The M66281FP is high speed line memory that uses high performance silicon gate CMOS process technology and  
adopts the FIFO (First In First Out) structure consisting of 5120 words × 8 bits × 2.  
Since memory is available to simultaneously output 1 line delay and 2 line delay data, the M66281FP is optimal for the  
compensation of data of multiple lines.  
Features  
Memory configuration:  
High speed cycle:  
High speed access:  
Output hold:  
5120 words × 8 bits × 2 (dynamic memory)  
25 ns (Min)  
18 ns (Max)  
3 ns (Min)  
Reading and writing operations can be completely carried out independently and asynchronously  
Variable length delay bit  
Input/output:  
Output:  
Q00 to Q07:  
Q10 to Q17:  
TTL direct connection allowable  
3 states  
1 line delay  
2 line delay  
Application  
Digital copying machine, laser beam printer, high speed facsimile, etc.  
Block Diagram  
Data inputs  
D0 to D7  
Data outputs  
Q0 to Q7  
Data outputs  
Q10 to Q17  
31 30 29 28 27 23 22 21  
Input buffer  
45 46 47  
2
3
4
5
6
9
10 11 12 13 16 17 18  
Output buffer  
REB  
36  
35  
34  
42  
41  
40  
WEB  
Read  
Write  
enable input  
enable input  
RRESB  
Read  
reset input  
WRESB  
Write  
reset input  
Memory array  
5120 words × 8 bits × 2  
Memory only for 1 line delay data  
Memory only for 2 line delay data  
(
)
RCK  
WCK  
Write  
clock input  
Read  
clock input  
VCC  
VCC  
VCC  
VCC  
8
7
GND  
GND  
GND  
GND  
19  
32  
44  
20  
33  
43  
REJ03F0254-0200 Rev.2.00 Sep 14, 2007  
Page 1 of 15  

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