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M66252FP PDF预览

M66252FP

更新时间: 2024-11-09 22:35:35
品牌 Logo 应用领域
三菱 - MITSUBISHI 存储光电二极管先进先出芯片
页数 文件大小 规格书
11页 147K
描述
1152 x 8-BIT LINE MEMORY FIFO

M66252FP 技术参数

是否Rohs认证: 不符合生命周期:Transferred
零件包装代码:SOIC包装说明:SOP, SOP24,.5
针数:24Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.66最长访问时间:40 ns
其他特性:LINE MEMORY周期时间:50 ns
JESD-30 代码:R-PDSO-G24JESD-609代码:e0
长度:15 mm内存密度:9216 bit
内存宽度:8功能数量:1
端子数量:24字数:1152 words
字数代码:1152工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:-20 °C
组织:1152X8输出特性:3-STATE
可输出:NO封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP24,.5
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:PARALLEL电源:5 V
认证状态:Not Qualified座面最大高度:2.4 mm
子类别:Other Memory ICs最大压摆率:0.1 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:8.4 mmBase Number Matches:1

M66252FP 数据手册

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MITSUBISHI DIGITALASSP
M66252P/FP
)  
1152 x 8-BIT LINE MEMORY (FIFO)  
DESCRIPTION  
PIN CONFIGURATION (TOP VIEW)  
The M66252P/FP is a high-speed line memory with a FIFO  
(First In First Out) structure of 1152-word × 8-bit configuration  
which uses high-performance silicon gate CMOS process  
technology.  
It has separate clock, enable and reset signals for write and  
read and is most suitable as a buffer memory between  
devices with different data processing throughput.  
Q
Q
Q
Q
0
1
2
3
1
2
3
24  
23  
22  
21  
D0  
D1  
D2  
D3  
Data output  
Data input  
4
Read enable input  
RE  
5
20 WE  
Write enable input  
6
19  
18  
Read reset input RRES  
GND  
WRES Write reset input  
FEATURES  
7
VCC  
• Memory construction ........................................................  
............................. 1152words x 8bits (dynamic memory)  
• High-speed cycle ............................................ 50ns (min.)  
• High-speed access ........................................ 40ns (max.)  
• Output hold ....................................................... 5ns (min.)  
• Fully independent, asynchronous write and read opera-  
tions  
Read clock input RCK  
8
9
17 WCK Write clock input  
Q
Q
Q
Q
4
5
6
7
16  
15  
14  
13  
D4  
D5  
D6  
D7  
10  
11  
12  
Data output  
Data input  
• Variable-length delay bit  
• Output.................................................................... 3-state  
24P4Y  
24P2W-A  
Outline  
APPLICATION  
Digital photocopiers, high-speed facsimiles, laser beam print-  
ers.  
BLOCK DIAGRAM  
Data input  
Data output  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6 Q7  
24 23 22 21 16 15 14 13  
1
2 3 4 9 10 11 12  
Input buffer  
Output buffer  
Write  
Read  
WE 20  
5 RE  
enable input  
enable input  
Memory array  
(1152 x 8 bits)  
Write  
Read  
WRES 19  
WCK 17  
6 RRES  
8 RCK  
reset input  
reset input  
Write  
Read  
clock input  
clock input  
Vcc 18  
7 GND  
1

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