Datasheet > M58LV064A150ZA1T

M58LV064A150ZA1T

更新时间： 2024-01-23 14:50:52

品牌	Logo	应用领域
恒忆 - NUMONYX		内存集成电路
页数	文件大小	规格书
65页	376K
描述
Flash, 4MX16, 150ns, PBGA64, 10 X 13 MM, 1 MM PITCH, TBGA-64

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M58LV064A150ZA1T 技术参数

是否Rohs认证：	符合	生命周期：	Transferred
零件包装代码：	BGA	包装说明：	10 X 13 MM, 1 MM PITCH, TBGA-64
针数：	64	Reach Compliance Code：	unknown
ECCN代码：	3A991.B.1.A	HTS代码：	8542.32.00.51
风险等级：	5.52	Is Samacsys：	N
最长访问时间：	150 ns	其他特性：	SYNCHRONOUS BURST MODE OPERATION ALSO POSSIBLE
命令用户界面：	YES	通用闪存接口：	YES
数据轮询：	NO	JESD-30 代码：	R-PBGA-B64
JESD-609代码：	e1	长度：	13 mm
内存密度：	67108864 bit	内存集成电路类型：	FLASH
内存宽度：	16	功能数量：	1
部门数/规模：	64	端子数量：	64
字数：	4194304 words	字数代码：	4000000
工作模式：	ASYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	4MX16
封装主体材料：	PLASTIC/EPOXY	封装代码：	TBGA
封装等效代码：	BGA64,8X8,40	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, THIN PROFILE	页面大小：	4 words
并行/串行：	PARALLEL	电源：	2/3.3,3.3 V
编程电压：	3 V	认证状态：	Not Qualified
就绪/忙碌：	YES	座面最大高度：	1.2 mm
部门规模：	1M	最大待机电流：	0.000001 A
子类别：	Flash Memories	最大压摆率：	0.05 mA
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
切换位：	NO	类型：	NOR TYPE
宽度：	10 mm	Base Number Matches：	1

M58LV064A150ZA1T 数据手册

M58LV064A, M58LV064B

SUMMARY DESCRIPTION

M58LV064 is a 64Mbit (4Mb x16 or 2Mb x32) non-

volatile memory that can be read, erased and re-

programmed. These operations can be performed

using a single low voltage (2.7V to 3.6V) core sup-

ply. On power-up the memory default to Read

mode with an asynchronous bus where it can be

read in the same way as a non-burst Flash mem-

ory.

The memory is divided into 64 blocks of 1Mbit that

can be erased independently so it is possible to

preserve valid data while old data is erased. Pro-

gram and Erase commands are written to the

Command Interface of the memory. An on-chip

Program/Erase Controller simplifies the process of

programming or erasing the memory by taking

care of all of the special operations that are re-

quired to update the memory contents. The end of

a Program or Erase operation can be detected and

any error conditions identified in the Status Regis-

ter. The command set required to control the

memory is consistent with JEDEC standards.

The Write Buffer allows the microprocessor to pro-

gram from 4 to 16 Words (or from 2 to 8 Double

Words) in parallel, both speeding up the program-

ming and freeing up the microprocessor to perform

other work. The minimum buffer size for a program

operation is a 4 Word (or 2 Double Word) page. A

page can only be programmed once between

Erase operations.

Erase can be suspended in order to perform either

Read or Program in any other block and then re-

sumed. Program can be suspended to Read data

in any other block and then resumed. Each block

can be programmed and erased over 100,000 cy-

cles.

tion status of each block is restored to the state

when power was last removed. Software com-

mands are provided to allow protection of some or

all of the blocks and to cancel all block protection

bits simultaneously. All Program or Erase opera-

tions are blocked when the Program Erase Enable

input Vpp is low.

The Reset/Power-Down pin is used to apply a

Hardware Reset to the memory and to set the de-

vice in deep power-down mode. It can also be

used to temporarily disable the protection mecha-

nism.

In asynchronous mode Chip Enable, Output En-

able and Write Enable signals control the bus op-

eration of the memory. An Address Latch input can

be used to latch addresses in Latch Controlled

mode. Together they allow simple, yet powerful,

connection to most microprocessors, often without

additional logic.

In synchronous mode all Bus Read operations are

synchronous with the Clock. Chip Enable and Out-

put Enable select the Bus Read operation; the ad-

dress is Latched using the Latch Enable inputs

and the address is advanced using Burst Address

Advance. The signals are compatible with most

microprocessor burst interfaces.

A One Time Programmable (OTP) area is included

for security purposes. Either 1K Words (x16 Bus

Width) or 1K Double-Words (x32 Bus Width) is

available in the OTP area. The process of reading

from and writing to the OTP area is not published

for security purposes; contact STMicroelectronics

for details on how to use the OTP area.

The memory is offered in various packages. The

M58LV064A is available in TSOP56 (14 x 20 mm)

and TBGA64 (1mm pitch). The M58LV064B is

available in TBGA80 (1mm pitch).

Individual block protection against Program or

Erase is provided for data security. All blocks are

protected during power-up. The protection of the

blocks is non-volatile; after power-up the protec-

6/65

1...3 4 567 8 9...65

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与M58LV064A150ZA1T相关器件

型号	品牌	描述	获取价格	数据表
M58LV064A150ZA6	NUMONYX	Flash, 4MX16, 150ns, PBGA64, 10 X 13 MM, 1 MM PITCH, TBGA-64	获取价格
M58LV064A150ZA6T	STMICROELECTRONICS	64 Mbit 4Mb x16 or 2Mb x32, Uniform Block, Burst 3V Supply Flash Memories	获取价格
M58LV064A150ZA6T	NUMONYX	Flash, 4MX16, 150ns, PBGA64, 10 X 13 MM, 1 MM PITCH, TBGA-64	获取价格
M58LV064B	STMICROELECTRONICS	64 Mbit 4Mb x16 or 2Mb x32, Uniform Block, Burst 3V Supply Flash Memories	获取价格
M58LV064B150N1T	STMICROELECTRONICS	64 Mbit 4Mb x16 or 2Mb x32, Uniform Block, Burst 3V Supply Flash Memories	获取价格
M58LV064B150N6T	STMICROELECTRONICS	64 Mbit 4Mb x16 or 2Mb x32, Uniform Block, Burst 3V Supply Flash Memories	获取价格

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