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M54HC165KT PDF预览

M54HC165KT

更新时间: 2024-11-25 13:10:07
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 移位寄存器
页数 文件大小 规格书
12页 321K
描述
Rad-Hard 8-bit PISO Shift Register

M54HC165KT 技术参数

生命周期:ActiveReach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
Factory Lead Time:30 weeks风险等级:5.68
Is Samacsys:N逻辑集成电路类型:PARALLEL IN SERIAL OUT
Base Number Matches:1

M54HC165KT 数据手册

 浏览型号M54HC165KT的Datasheet PDF文件第2页浏览型号M54HC165KT的Datasheet PDF文件第3页浏览型号M54HC165KT的Datasheet PDF文件第4页浏览型号M54HC165KT的Datasheet PDF文件第5页浏览型号M54HC165KT的Datasheet PDF文件第6页浏览型号M54HC165KT的Datasheet PDF文件第7页 
M54HC165  
RAD-HARD 8 BIT PISO SHIFT REGISTER  
HIGH SPEED:  
= 15ns (TYP.) at V  
t
= 6V  
CC  
PD  
LOW POWER DISSIPATION:  
=4µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28% V (MIN.)  
V
NIH  
NIL  
CC  
DILC-16  
FPC-16  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
FM  
EM  
V
CC  
DILC  
FPC  
M54HC165D  
M54HC165K  
M54HC165D1  
M54HC165K1  
PIN AND FUNCTION COMPATIBLE WITH  
54 SERIES 165  
SPACE GRADE-1: ESA SCC QUALIFIED  
50 krad QUALIFIED, 100 krad AVAILABLE ON  
REQUEST  
NO SEL UNDER HIGH LET HEAVY IONS  
IRRADIATION  
when the shift/load input is low. The parallel data  
can change while shift/load is low, provided that  
the recommended set-up and hold times are  
observed. For clocked operation, shift/load must  
be high. The two clock input perform identically;  
one can be used as a clock inhibit by applying a  
high signal; to permit this operation clocking is  
accomplished through a 2 input nor gate.  
DEVICE FULLY COMPLIANT WITH  
SCC-9306-042  
DESCRIPTION  
To avoid double clocking, however, the inhibit  
signal should only go high while the clock is high.  
Otherwise the rising inhibit signal will cause the  
same response as rising clock edge.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
The M54HC165 is an high speed CMOS 8 BIT  
PISO SHIFT REGISTER fabricated with silicon  
gate C MOS technology.  
This device contains eight clocked master slave  
RS flip-flops connected as a shift register, with  
2
auxiliary  
gating  
to  
provide  
over-riding  
asynchronous parallel entry. Parallel data enters  
PIN CONNECTION  
March 2004  
1/12  

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