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M54HC166 PDF预览

M54HC166

更新时间: 2024-09-30 22:46:39
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 移位寄存器
页数 文件大小 规格书
13页 272K
描述
8 BIT PISO SHIFT REGISTER

M54HC166 数据手册

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M54HC166  
M74HC166  
8 BIT PISO SHIFT REGISTER  
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HIGH SPEED  
fMAX = 57 MHz (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
|IOH| = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE WITH  
54/74LS166  
ORDER CODES :  
M54HC166F1R  
M74HC166B1R  
M74HC166M1R  
M74HC166C1R  
PIN CONNECTIONS (top view)  
DESCRIPTION  
The M54/74HC166 is a high speed C2MOS 8 BIT  
PISO SHIFT REGISTER fabricated in silicon gate  
C2MOS technology. It has the same highspeed per-  
formance of LSTTL combined with true CMOS low  
power consumption.  
It consists of parallel or serial inputs and a serial-out  
8-bit shift register with gated clock inputs and an  
overriding clear input. The parallel-in or serial-in  
modes are controlled by the SHIFT/LOAD input.  
When the SHIFT/LOAD input is held high, the serial  
data input is enabled and the eight flip-flops perform  
serial shifting with each clock pulse. When held low,  
the parallel data inputs are enabled and syn-  
chronous loading occurs on the next clock pulse.  
Clocking is accomplished on the low-to-high level  
edge of the clock pulse. The CLOCK-INHIBIT input  
should be changed to the high only while the  
CLOCK input is held high. A direct clear input over-  
rides all other inputs, including the clock, and sets  
all flip-flops to zero. Functional details are shown in  
the truth table and the timing chart.  
NC =  
No Inter-  
nal Con-  
All inputs are equipped with protection circuits  
against static discharge and transient excess volt-  
age.  
October 1992  
1/13  

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