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M54HC166D PDF预览

M54HC166D

更新时间: 2024-11-25 05:00:59
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 移位寄存器
页数 文件大小 规格书
11页 337K
描述
RAD-HARD 8 BIT PISO SHIFT REGISTER

M54HC166D 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP16,.3针数:16
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.17计数方向:RIGHT
系列:HC/UHJESD-30 代码:R-CDIP-T16
JESD-609代码:e0长度:20.32 mm
逻辑集成电路类型:PARALLEL IN SERIAL OUT最大频率@ Nom-Sup:21000000 Hz
位数:8功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:TRUE
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 V传播延迟(tpd):225 ns
认证状态:Not Qualified座面最大高度:3.83 mm
子类别:Shift Registers最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:7.62 mm
最小 fmax:25 MHzBase Number Matches:1

M54HC166D 数据手册

 浏览型号M54HC166D的Datasheet PDF文件第2页浏览型号M54HC166D的Datasheet PDF文件第3页浏览型号M54HC166D的Datasheet PDF文件第4页浏览型号M54HC166D的Datasheet PDF文件第5页浏览型号M54HC166D的Datasheet PDF文件第6页浏览型号M54HC166D的Datasheet PDF文件第7页 
M54HC166  
RAD-HARD 8 BIT PISO SHIFT REGISTER  
HIGH SPEED:  
= 63 MHz (TYP.) at V = 6V  
f
MAX  
CC  
LOW POWER DISSIPATION:  
=4µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28% V (MIN.)  
V
NIH  
NIL  
CC  
DILC-16  
FPC-16  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
FM  
EM  
V
CC  
DILC  
FPC  
M54HC166D  
M54HC166K  
M54HC166D1  
M54HC166K1  
PIN AND FUNCTION COMPATIBLE WITH  
54 SERIES 166  
SPACE GRADE-1: ESA SCC QUALIFIED  
50 krad QUALIFIED, 100 krad AVAILABLE ON  
REQUEST  
NO SEL UNDER HIGH LET HEAVY IONS  
IRRADIATION  
input. When the SHIFT/LOAD input is held high,  
the serial data input is enabled and the eight  
flip-flops perform serial shifting with each clock  
pulse; when held low, the parallel data inputs are  
enabled and synchronous loading occurs on the  
next clock pulse. Clocking is accomplished on the  
low-to-high level edge of the clock pulse. The  
CLOCK-INHIBIT input should be changed to the  
high only while the clock input is held high. A direct  
clear input overrides all other inputs, including the  
clock, and sets all flip-flops to zero. Functional  
details are shown in the truth table and the timing  
chart. All inputs are equipped with protection  
circuits against static discharge and transient  
excess voltage.  
DEVICE FULLY COMPLIANT WITH  
SCC-9306-043  
DESCRIPTION  
The M54HC166 is an high speed CMOS 8 BIT  
PISO SHIFT REGISTER fabricated with silicon  
2
gate C MOS technology.  
It consists of parallel or serial inputs and a  
serial-out 8 bit shift register with gated clock inputs  
and an overriding clear input. The parallel-in or  
serial-in modes are controlled by the SHIFT/LOAD  
PIN CONNECTION  
March 2004  
1/11  

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