Datasheet > M2004-01-669.3266

M2004-01-669.3266

更新时间： 2024-11-29 20:17:11

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
10页	1539K
描述
PLL/Frequency Synthesis Circuit

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技术参数
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M2004-01-669.3266 技术参数

生命周期：	Active	包装说明：	,
Reach Compliance Code：	compliant	风险等级：	5.65
Is Samacsys：	N	Base Number Matches：	1

M2004-01-669.3266 数据手册

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M2004-01

Micro Networks

An Integrated Circuit Systems Company

Preliminary Specifications

M2004-01

Frequency Synthesizer

DESCRIPTION

The M2004-01 integrates a high performance Phase

Locked Loop (PLL) with a Voltage Controlled SAW

Oscillator (VCSO) to provide a low jitter Frequency

Translator in a 9mm x 9mm surface mount package.

The internal high “Q” SAW filter provides low jitter

signal performance and determines the maximum

output frequency of the VCSO. A programmable

output divider can divide the VCSO frequency to

achieve an output as low as 38.88MHz.

The input to the Frequency Translator is provided by

selecting between one of two output reference

clocks. The output frequency is an integer multiple

of the input reference frequency.

FEATURES

Output Clock Frequency up to 700MHz

Differential LVPECL Outputs

Internal Low-jitter SAW-based Oscillator

Intrinsic Jitter <1ps rms (12kHz - 20MHz)

Jitter Attenuation of Input Reference Clock

Dual Input MUX

Parallel and serial control of the output and

feedback dividers is provided via the configuration

logic. An external loop filter sets the PLL bandwidth

which can be optimized to provide jitter attenuation

of the input reference clock.

Parallel Programming

Tunable Loop Filter Response

Differential LVPECL Outputs

3.3V Operation

The M2004-01 is available at SONET/SDH and

10GbE frequencies up to 700MHz.

Small 9mm x 9mm SMT Package

APPLICATIONS

ABSOLUTE MAX RATINGS

SONET / SDH / 10GbE System

Synchronization

Inputs, V_I:

................................................. -0.5 to V_CC+0.5V

Output, V_O: ................................................. -0.5 to V_CC+0.5V

Supply Voltage, V_DD: ......................................................... 4.6 V

Storage Temperature, T_STO:............................ -45°C to +100°C

Add / Drop Muxes, Access and Edge

Switches

Line Card System Clock Cleaner /

Translator

Stresses beyond those listed under Absolute Maximum Ratings may cause

permanent damage to the device. These ratings are stress specifications

only. Functional operation of product at these conditions or any conditions

beyond those listed in the DC Characteristics or AC Characteristics is not

implied. Exposure to absolute maximum rating conditions for extended peri-

ods may affect product reliability.

Optical Module Clock Cleaner / Translator

ISO 9001

Registered

Micro Networks

324 Clark Street

Worcester, MA 01606

tel: 508-852-5400

fax: 508-852-8456

www.micronetworks.com

12 3 4 5 6 7...10

中文翻译

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与M2004-01-669.3266相关器件

型号	品牌	获取价格	描述	数据表
M2004-01-672.1600	ICSI	获取价格	Frequency Synthesizer
M2004-01-672.1600	IDT	获取价格	PLL/Frequency Synthesis Circuit
M2004-01-690.5692	ICSI	获取价格	Frequency Synthesizer
M2004-01-690.5692	IDT	获取价格	PLL/Frequency Synthesis Circuit
M2004-01-693.4830	ICSI	获取价格	Frequency Synthesizer
M2004-01-AG	SPECTRUM	获取价格	Support Circuit, 1-Func, 9 X 9 MM, SMT-36
M2004-01I400.0000T	IDT	获取价格	CLCC-36, Reel
M2004-01I622.0800T	IDT	获取价格	CLCC-36, Reel
M2004-01I640.0000	IDT	获取价格	CLCC-36, Tube
M2004-02	ICSI	获取价格	Frequency Synthesizer

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