P r e l i m i n a r y I n f o r m a t i o n
Integrated
Circuit
Systems, Inc.
M1033/34
VCSO BASED CLOCK PLL WITH AUTOSWITCH
GENERAL DESCRIPTION
The M1033/34 is a VCSO (Voltage Controlled SAW
Oscillator) based clock jitter
PIN ASSIGNMENT (9 x 9 mm SMT)
attenuator PLL designed for clock
jitter attenuation and frequency
translation. The device is ideal for
generating the transmit reference
clock for optical network systems
supporting up to 2.5Gb data rates.
It can serve to jitter attenuate a
MR_SEL2
MR_SEL0
MR_SEL1
LOR
P_SEL0
P_SEL1
nFOUT
FOUT
28
29
30
31
32
33
34
35
36
18
17
16
15
14
13
12
11
10
M1033
M1034
NBW
VCC
GND
stratum reference clock or a recovered clock in loop
timing mode. The M1033/34 module includes a
proprietary SAW (surface acoustic wave) delay line as
part of the VCSO. This results in a high frequency,
high-Q, low phase noise oscillator that assures low
intrinsic output jitter.
REF_ACK
AUTO
VCC
( T o p V i e w )
DNC
DNC
DNC
GND
FEATURES
◆ Integrated SAW delay line; low phase jitter of < 0.5ps
rms, typical (12kHz to 20MHz)
Figure 1: Pin Assignment
◆ Output frequencies of 62.5 to 175 MHz
(Specify VCSO output frequency at time of order)
Example I/O Clock Frequency Combinations
Using M1033-11-155.5200 or M1034-11-155.5200
◆ LVPECL clock output (CML and LVDS options available)
◆ Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
PLL Ratio
(Pin Selectable)
Output Clock
Input Reference
Clock (MHz)
◆ Loss of Reference (LOR) output pin; Narrow Bandwidth
control input (NBW pin)
(MHz)
(Pin Selectable)
(M1033)
(M1034)
(M1033) (M1034)
◆ AutoSwitch (AUTO pin) - automatic (non-revertive)
reference clock reselection upon clock failure
19.44 or 38.88
77.76
8 or 4
2
1
155.52
or
77.76
◆ Acknowledge pin (REF_ACK pin) indicates the actively
selected reference input
155.52
622.08
0.25
◆ Phase Build-out only upon MUX reselection option
(PBOM)
Table 1: Example I/O Clock Frequency Combinations
◆ Pin-selectable feedback and reference divider ratios
◆ Single 3.3V power supply
◆ Small 9 x 9 mm SMT (surface mount) package
SIMPLIFIED BLOCK DIAGRAM
Loop Filter
M1033/34
NBW
MUX
PLL
DIF_REF0
nDIF_REF0
Activity
Detector
0
Phase
Detector
R Div
DIF_REF1
nDIF_REF1
Activity
Detector
1
VCSO
0
1
M Divider
LOR
REF_ACK
FOUT
nFOUT
Auto
Ref Sel
P Divider
TriState
(1, 2, or TriState)
1
0
REF_SEL
AUTO
M / R Divider
LUT
4
2
MR_SEL3:0
P_SEL1:0
P Divider
LUT
Figure 2: Simplified Block Diagram
M1033/34 Preliminary Information 0.1
Revised 07Apr2005
M1033/34 VCSO Based Clock PLL with AutoSwitch
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400