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M1034-11I161.1328 PDF预览

M1034-11I161.1328

更新时间： 2024-01-03 15:17:58
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
14页 200K
描述
PLL Based Clock Driver, 1034 Series, 1 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9 MM, CERAMIC, LCC-36

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M1034-11I161.1328 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：LCC
包装说明：9 X 9 MM, CERAMIC, LCC-36针数：36
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.84系列：1034
输入调节：DIFFERENTIALJESD-30 代码：S-CQCC-N36
JESD-609代码：e3长度：8.99 mm
逻辑集成电路类型：PLL BASED CLOCK DRIVER功能数量：1
反相输出次数：端子数量：36
实输出次数：1最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：QCCN
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：3.1 mm最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：MATTE TIN端子形式：NO LEAD
端子节距：0.635 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：8.99 mm
最小 fmax：175 MHzBase Number Matches：1

M1034-11I161.1328 数据手册

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P r e l i m i n a r y I n f o r m a t i o n  
Integrated  
Circuit  
Systems, Inc.  
M1033/34  
VCSO BASED CLOCK PLL WITH AUTOSWITCH  
GENERAL DESCRIPTION  
The M1033/34 is a VCSO (Voltage Controlled SAW  
Oscillator) based clock jitter  
PIN ASSIGNMENT (9 x 9 mm SMT)  
attenuator PLL designed for clock  
jitter attenuation and frequency  
translation. The device is ideal for  
generating the transmit reference  
clock for optical network systems  
supporting up to 2.5Gb data rates.  
It can serve to jitter attenuate a  
MR_SEL2  
MR_SEL0  
MR_SEL1  
LOR  
P_SEL0  
P_SEL1  
nFOUT  
FOUT  
28  
29  
30  
31  
32  
33  
34  
35  
36  
18  
17  
16  
15  
14  
13  
12  
11  
10  
M1033  
M1034  
NBW  
VCC  
GND  
stratum reference clock or a recovered clock in loop  
timing mode. The M1033/34 module includes a  
proprietary SAW (surface acoustic wave) delay line as  
part of the VCSO. This results in a high frequency,  
high-Q, low phase noise oscillator that assures low  
intrinsic output jitter.  
REF_ACK  
AUTO  
VCC  
( T o p V i e w )  
DNC  
DNC  
DNC  
GND  
FEATURES  
◆ Integrated SAW delay line; low phase jitter of < 0.5ps  
rms, typical (12kHz to 20MHz)  
Figure 1: Pin Assignment  
◆ Output frequencies of 62.5 to 175 MHz  
(Specify VCSO output frequency at time of order)  
Example I/O Clock Frequency Combinations  
Using M1033-11-155.5200 or M1034-11-155.5200  
◆ LVPECL clock output (CML and LVDS options available)  
◆ Reference clock inputs support differential LVDS,  
LVPECL, as well as single-ended LVCMOS, LVTTL  
PLL Ratio  
(Pin Selectable)  
Output Clock  
Input Reference  
Clock (MHz)  
◆ Loss of Reference (LOR) output pin; Narrow Bandwidth  
control input (NBW pin)  
(MHz)  
(Pin Selectable)  
(M1033)  
(M1034)  
(M1033) (M1034)  
◆ AutoSwitch (AUTO pin) - automatic (non-revertive)  
reference clock reselection upon clock failure  
19.44 or 38.88  
77.76  
8 or 4  
2
1
155.52  
or  
77.76  
◆ Acknowledge pin (REF_ACK pin) indicates the actively  
selected reference input  
155.52  
622.08  
0.25  
◆ Phase Build-out only upon MUX reselection option  
(PBOM)  
Table 1: Example I/O Clock Frequency Combinations  
◆ Pin-selectable feedback and reference divider ratios  
◆ Single 3.3V power supply  
◆ Small 9 x 9 mm SMT (surface mount) package  
SIMPLIFIED BLOCK DIAGRAM  
Loop Filter  
M1033/34  
NBW  
MUX  
PLL  
DIF_REF0  
nDIF_REF0  
Activity  
Detector  
0
Phase  
Detector  
R Div  
DIF_REF1  
nDIF_REF1  
Activity  
Detector  
1
VCSO  
0
1
M Divider  
LOR  
REF_ACK  
FOUT  
nFOUT  
Auto  
Ref Sel  
P Divider  
TriState  
(1, 2, or TriState)  
1
0
REF_SEL  
AUTO  
M / R Divider  
LUT  
4
2
MR_SEL3:0  
P_SEL1:0  
P Divider  
LUT  
Figure 2: Simplified Block Diagram  
M1033/34 Preliminary Information 0.1  
Revised 07Apr2005  
M1033/34 VCSO Based Clock PLL with AutoSwitch  
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400  
1234567...14

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